phy/micrel: add ability to support 50MHz RMII clock on KZS8051RNL

Platform code can now set the MICREL_PHY_50MHZ_CLK bit of dev_flags in a fixup routine (registered with phy_register_fixup_for_uid()), to make the KZS8051RNL PHY work with 50MHz RMII reference clock. Cc: David J. Choi <david.choi@micrel.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: David S. Miller <davem@davemloft.net>

phy/micrel: add ability to support 50MHz RMII clock on KZS8051RNL
Platform code can now set the MICREL_PHY_50MHZ_CLK bit of dev_flags in a fixup routine (registered with phy_register_fixup_for_uid()), to make the KZS8051RNL PHY work with 50MHz RMII reference clock. Cc: David J. Choi <david.choi@micrel.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: David S. Miller <davem@davemloft.net>
Baruch Siach · David S. Miller
1 parent 68aa3fd551
Showing 2 changed files with 32 additions and 8 deletions Side-by-side Diff
drivers/net/phy/micrel.c
include/linux/micrel_phy.h
@@ -19,14 +19,8 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/phy.h>
+#include <linux/micrel_phy.h>
  
-#define	PHY_ID_KSZ9021			0x00221611
-#define	PHY_ID_KS8737			0x00221720
-#define	PHY_ID_KS8041			0x00221510
-#define	PHY_ID_KS8051			0x00221550
-/* both for ks8001 Rev. A/B, and for ks8721 Rev 3. */
-#define	PHY_ID_KS8001			0x0022161A
-
 /* general Interrupt control/status reg in vendor specific block. */
 #define MII_KSZPHY_INTCS			0x1B
 #define	KSZPHY_INTCS_JABBER			(1 << 15)
@@ -46,6 +40,7 @@
 #define KSZPHY_CTRL_INT_ACTIVE_HIGH		(1 << 9)
 #define KSZ9021_CTRL_INT_ACTIVE_HIGH		(1 << 14)
 #define KS8737_CTRL_INT_ACTIVE_HIGH		(1 << 14)
+#define KSZ8051_RMII_50MHZ_CLK			(1 << 7)
  
 static int kszphy_ack_interrupt(struct phy_device *phydev)
 {
@@ -106,6 +101,19 @@
 	return 0;
 }
  
+static int ks8051_config_init(struct phy_device *phydev)
+{
+	int regval;
+
+	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
+		regval = phy_read(phydev, MII_KSZPHY_CTRL);
+		regval |= KSZ8051_RMII_50MHZ_CLK;
+		phy_write(phydev, MII_KSZPHY_CTRL, regval);
+	}
+
+	return 0;
+}
+
 static struct phy_driver ks8737_driver = {
 	.phy_id		= PHY_ID_KS8737,
 	.phy_id_mask	= 0x00fffff0,
@@ -142,7 +150,7 @@
 	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause
 				| SUPPORTED_Asym_Pause),
 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
-	.config_init	= kszphy_config_init,
+	.config_init	= ks8051_config_init,
 	.config_aneg	= genphy_config_aneg,
 	.read_status	= genphy_read_status,
 	.ack_interrupt	= kszphy_ack_interrupt,
+#ifndef _MICREL_PHY_H
+#define _MICREL_PHY_H
+
+#define MICREL_PHY_ID_MASK	0x00fffff0
+
+#define PHY_ID_KSZ9021		0x00221611
+#define PHY_ID_KS8737		0x00221720
+#define PHY_ID_KS8041		0x00221510
+#define PHY_ID_KS8051		0x00221550
+/* both for ks8001 Rev. A/B, and for ks8721 Rev 3. */
+#define PHY_ID_KS8001		0x0022161A
+
+/* struct phy_device dev_flags definitions */
+#define MICREL_PHY_50MHZ_CLK	0x00000001
+
+#endif /* _MICREL_PHY_H */
...	...	@@ -19,14 +19,8 @@
19	19	#include <linux/kernel.h>
20	20	#include <linux/module.h>
21	21	#include <linux/phy.h>
	22	+#include <linux/micrel_phy.h>
22	23
23		-#define PHY_ID_KSZ9021 0x00221611
24		-#define PHY_ID_KS8737 0x00221720
25		-#define PHY_ID_KS8041 0x00221510
26		-#define PHY_ID_KS8051 0x00221550
27		-/* both for ks8001 Rev. A/B, and for ks8721 Rev 3. */
28		-#define PHY_ID_KS8001 0x0022161A
29		-
30	24	/* general Interrupt control/status reg in vendor specific block. */
31	25	#define MII_KSZPHY_INTCS 0x1B
32	26	#define KSZPHY_INTCS_JABBER (1 << 15)
...	...	@@ -46,6 +40,7 @@
46	40	#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
47	41	#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
48	42	#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
	43	+#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
49	44
50	45	static int kszphy_ack_interrupt(struct phy_device *phydev)
51	46	{
...	...	@@ -106,6 +101,19 @@
106	101	return 0;
107	102	}
108	103
	104	+static int ks8051_config_init(struct phy_device *phydev)
	105	+{
	106	+ int regval;
	107	+
	108	+ if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
	109	+ regval = phy_read(phydev, MII_KSZPHY_CTRL);
	110	+ regval \|= KSZ8051_RMII_50MHZ_CLK;
	111	+ phy_write(phydev, MII_KSZPHY_CTRL, regval);
	112	+ }
	113	+
	114	+ return 0;
	115	+}
	116	+
109	117	static struct phy_driver ks8737_driver = {
110	118	.phy_id = PHY_ID_KS8737,
111	119	.phy_id_mask = 0x00fffff0,
...	...	@@ -142,7 +150,7 @@
142	150	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause
143	151	\| SUPPORTED_Asym_Pause),
144	152	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
145		- .config_init = kszphy_config_init,
	153	+ .config_init = ks8051_config_init,
146	154	.config_aneg = genphy_config_aneg,
147	155	.read_status = genphy_read_status,
148	156	.ack_interrupt = kszphy_ack_interrupt,
	1	+#ifndef _MICREL_PHY_H
	2	+#define _MICREL_PHY_H
	3	+
	4	+#define MICREL_PHY_ID_MASK 0x00fffff0
	5	+
	6	+#define PHY_ID_KSZ9021 0x00221611
	7	+#define PHY_ID_KS8737 0x00221720
	8	+#define PHY_ID_KS8041 0x00221510
	9	+#define PHY_ID_KS8051 0x00221550
	10	+/* both for ks8001 Rev. A/B, and for ks8721 Rev 3. */
	11	+#define PHY_ID_KS8001 0x0022161A
	12	+
	13	+/* struct phy_device dev_flags definitions */
	14	+#define MICREL_PHY_50MHZ_CLK 0x00000001
	15	+
	16	+#endif /* _MICREL_PHY_H */