Davinci: psc - use ioremap()

This patch modifies the psc and clock control code to use ioremap()ed registers. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>

Davinci: psc - use ioremap()
This patch modifies the psc and clock control code to use ioremap()ed registers. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Cyril Chemparathy · Kevin Hilman
1 parent 1bcd38ad2d
Showing 9 changed files with 23 additions and 26 deletions Side-by-side Diff
arch/arm/mach-davinci/clock.c
arch/arm/mach-davinci/da830.c
arch/arm/mach-davinci/da850.c
arch/arm/mach-davinci/dm355.c
arch/arm/mach-davinci/dm365.c
arch/arm/mach-davinci/dm644x.c
arch/arm/mach-davinci/dm646x.c
arch/arm/mach-davinci/include/mach/common.h
arch/arm/mach-davinci/psc.c
@@ -302,7 +302,6 @@
 	struct pll_data *pll = clk->pll_data;
 	unsigned long rate = clk->rate;
  
-	pll->base = IO_ADDRESS(pll->phys_base);
 	ctrl = __raw_readl(pll->base + PLLCTL);
 	rate = pll->input_rate = clk->parent->rate;
  
@@ -458,8 +457,17 @@
 				clk->recalc = clk_leafclk_recalc;
 		}
  
-		if (clk->pll_data && !clk->pll_data->div_ratio_mask)
-			clk->pll_data->div_ratio_mask = PLLDIV_RATIO_MASK;
+		if (clk->pll_data) {
+			struct pll_data *pll = clk->pll_data;
+
+			if (!pll->div_ratio_mask)
+				pll->div_ratio_mask = PLLDIV_RATIO_MASK;
+
+			if (pll->phys_base && !pll->base) {
+				pll->base = ioremap(pll->phys_base, SZ_4K);
+				WARN_ON(!pll->base);
+			}
+		}
  
 		if (clk->recalc)
 			clk->rate = clk->recalc(clk);
@@ -1127,10 +1127,7 @@
 	},
 };
  
-static void __iomem *da830_psc_bases[] = {
-	IO_ADDRESS(DA8XX_PSC0_BASE),
-	IO_ADDRESS(DA8XX_PSC1_BASE),
-};
+static u32 da830_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
  
 /* Contents of JTAG ID register used to identify exact cpu type */
 static struct davinci_id da830_ids[] = {
@@ -782,10 +782,7 @@
 	},
 };
  
-static void __iomem *da850_psc_bases[] = {
-	IO_ADDRESS(DA8XX_PSC0_BASE),
-	IO_ADDRESS(DA8XX_PSC1_BASE),
-};
+static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
  
 /* Contents of JTAG ID register used to identify exact cpu type */
 static struct davinci_id da850_ids[] = {
@@ -783,9 +783,7 @@
 	},
 };
  
-static void __iomem *dm355_psc_bases[] = {
-	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
-};
+static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
  
 /*
  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
@@ -1002,9 +1002,7 @@
 	},
 };
  
-static void __iomem *dm365_psc_bases[] = {
-	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
-};
+static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
  
 static struct davinci_timer_info dm365_timer_info = {
 	.timers		= davinci_timer_instance,
@@ -674,9 +674,7 @@
 	},
 };
  
-static void __iomem *dm644x_psc_bases[] = {
-	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
-};
+static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
  
 /*
  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
@@ -758,9 +758,7 @@
 	},
 };
  
-static void __iomem *dm646x_psc_bases[] = {
-	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
-};
+static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
  
 /*
  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
@@ -49,7 +49,7 @@
 	struct davinci_id		*ids;
 	unsigned long			ids_num;
 	struct clk_lookup		*cpu_clks;
-	void __iomem			**psc_bases;
+	u32				*psc_bases;
 	unsigned long			psc_bases_num;
 	void __iomem			*pinmux_base;
 	const struct mux_config		*pinmux_pins;
@@ -38,8 +38,9 @@
 		return 0;
 	}
  
-	psc_base = soc_info->psc_bases[ctlr];
+	psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
 	mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
+	iounmap(psc_base);
  
 	/* if clocked, state can be "Enable" or "SyncReset" */
 	return mdstat & BIT(12);
@@ -59,7 +60,7 @@
 		return;
 	}
  
-	psc_base = soc_info->psc_bases[ctlr];
+	psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
  
 	mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
 	mdctl &= ~MDSTAT_STATE_MASK;
@@ -99,5 +100,7 @@
 	do {
 		mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
 	} while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
+
+	iounmap(psc_base);
 }
...	...	@@ -302,7 +302,6 @@
302	302	struct pll_data *pll = clk->pll_data;
303	303	unsigned long rate = clk->rate;
304	304
305		- pll->base = IO_ADDRESS(pll->phys_base);
306	305	ctrl = __raw_readl(pll->base + PLLCTL);
307	306	rate = pll->input_rate = clk->parent->rate;
308	307
...	...	@@ -458,8 +457,17 @@
458	457	clk->recalc = clk_leafclk_recalc;
459	458	}
460	459
461		- if (clk->pll_data && !clk->pll_data->div_ratio_mask)
462		- clk->pll_data->div_ratio_mask = PLLDIV_RATIO_MASK;
	460	+ if (clk->pll_data) {
	461	+ struct pll_data *pll = clk->pll_data;
	462	+
	463	+ if (!pll->div_ratio_mask)
	464	+ pll->div_ratio_mask = PLLDIV_RATIO_MASK;
	465	+
	466	+ if (pll->phys_base && !pll->base) {
	467	+ pll->base = ioremap(pll->phys_base, SZ_4K);
	468	+ WARN_ON(!pll->base);
	469	+ }
	470	+ }
463	471
464	472	if (clk->recalc)
465	473	clk->rate = clk->recalc(clk);
...	...	@@ -1127,10 +1127,7 @@
1127	1127	},
1128	1128	};
1129	1129
1130		-static void __iomem *da830_psc_bases[] = {
1131		- IO_ADDRESS(DA8XX_PSC0_BASE),
1132		- IO_ADDRESS(DA8XX_PSC1_BASE),
1133		-};
	1130	+static u32 da830_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
1134	1131
1135	1132	/* Contents of JTAG ID register used to identify exact cpu type */
1136	1133	static struct davinci_id da830_ids[] = {
...	...	@@ -782,10 +782,7 @@
782	782	},
783	783	};
784	784
785		-static void __iomem *da850_psc_bases[] = {
786		- IO_ADDRESS(DA8XX_PSC0_BASE),
787		- IO_ADDRESS(DA8XX_PSC1_BASE),
788		-};
	785	+static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
789	786
790	787	/* Contents of JTAG ID register used to identify exact cpu type */
791	788	static struct davinci_id da850_ids[] = {
...	...	@@ -783,9 +783,7 @@
783	783	},
784	784	};
785	785
786		-static void __iomem *dm355_psc_bases[] = {
787		- IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
788		-};
	786	+static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
789	787
790	788	/*
791	789	* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
...	...	@@ -1002,9 +1002,7 @@
1002	1002	},
1003	1003	};
1004	1004
1005		-static void __iomem *dm365_psc_bases[] = {
1006		- IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
1007		-};
	1005	+static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
1008	1006
1009	1007	static struct davinci_timer_info dm365_timer_info = {
1010	1008	.timers = davinci_timer_instance,
...	...	@@ -674,9 +674,7 @@
674	674	},
675	675	};
676	676
677		-static void __iomem *dm644x_psc_bases[] = {
678		- IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
679		-};
	677	+static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
680	678
681	679	/*
682	680	* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
...	...	@@ -758,9 +758,7 @@
758	758	},
759	759	};
760	760
761		-static void __iomem *dm646x_psc_bases[] = {
762		- IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
763		-};
	761	+static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
764	762
765	763	/*
766	764	* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
...	...	@@ -49,7 +49,7 @@
49	49	struct davinci_id *ids;
50	50	unsigned long ids_num;
51	51	struct clk_lookup *cpu_clks;
52		- void __iomem **psc_bases;
	52	+ u32 *psc_bases;
53	53	unsigned long psc_bases_num;
54	54	void __iomem *pinmux_base;
55	55	const struct mux_config *pinmux_pins;
...	...	@@ -38,8 +38,9 @@
38	38	return 0;
39	39	}
40	40
41		- psc_base = soc_info->psc_bases[ctlr];
	41	+ psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
42	42	mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
	43	+ iounmap(psc_base);
43	44
44	45	/* if clocked, state can be "Enable" or "SyncReset" */
45	46	return mdstat & BIT(12);
...	...	@@ -59,7 +60,7 @@
59	60	return;
60	61	}
61	62
62		- psc_base = soc_info->psc_bases[ctlr];
	63	+ psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
63	64
64	65	mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
65	66	mdctl &= ~MDSTAT_STATE_MASK;
...	...	@@ -99,5 +100,7 @@
99	100	do {
100	101	mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
101	102	} while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
	103	+
	104	+ iounmap(psc_base);
102	105	}