Eric Lee / smarc-fsl-linux-kernel

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Commit f3c677b997757326e1f29d33060719a6a5091950

Authored by Forrest Shi
Committed by Dan Williams
1 parent c989a7fc13
Exists in master and in 39 other branches 8mp-imx_5.4.70_2.3.0, 8qm-imx_5.4.70_2.3.0, emb_imx_lf-5.15.y, emb_lf-6.1.y, imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, imx_4.1.15_1.0.0_ga, pitx_8mp_lf-5.10.y, rt-smarc-imx_4.1.15_1.0.0_ga, rt_linux_5.15.71, smarc-8m-android-11.0.0_2.0.0, smarc-imx6_4.14.98_2.0.0_ga, smarc-imx6_4.9.88_2.0.0_ga, smarc-imx7_4.14.98_2.0.0_ga, smarc-imx7_4.9.11_1.0.0_ga, smarc-imx7_4.9.88_2.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-imx_4.1.15_1.0.0_ga, smarc-imx_4.9.11_1.0.0_ga, smarc-imx_4.9.51_imx8m_ga, smarc-imx_4.9.88_2.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_1.2.0_ga, smarc_8m_00d0_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.14.78_1.0.0_ga, smarc_8m_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.19.35_1.1.0, smarc_8mm_imx_4.14.78_1.0.0_ga, smarc_8mm_imx_4.14.98_2.0.0_ga, smarc_8mm_imx_4.19.35_1.1.0, smarc_8mm_imx_5.4.24_2.1.0, smarc_8mp_lf-5.10.y, smarc_8mq_imx_5.4.24_2.1.0, smarc_8mq_lf-5.10.y, smarc_imx_lf-5.15.y

fsldma: fix issue of slow dma 

Fixed fsl dma slow issue by initializing dma mode register with
bandwidth control. It boosts dma performance and should works
with 85xx board.

Signed-off-by: Forrest Shi <b29237@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

Showing 2 changed files with 12 additions and 3 deletions Side-by-side Diff

drivers/dma/fsldma.c
Diff comments   View file @ f3c677b
... ... @@ -50,9 +50,11 @@
50 50 * EIE - Error interrupt enable
51 51 * EOSIE - End of segments interrupt enable (basic mode)
52 52 * EOLNIE - End of links interrupt enable
  53 + * BWC - Bandwidth sharing among channels
53 54 */
54   - DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
55   - | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
  55 + DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
  56 + | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
  57 + | FSL_DMA_MR_EOSIE, 32);
56 58 break;
57 59 case FSL_DMA_IP_83XX:
58 60 /* Set the channel to below modes:
drivers/dma/fsldma.h
Diff comments   View file @ f3c677b
1 1 /*
2   - * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
  2 + * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
3 3 *
4 4 * Author:
5 5 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
... ... @@ -35,6 +35,13 @@
35 35 #define FSL_DMA_MR_EMS_EN 0x00040000
36 36 #define FSL_DMA_MR_DAHE 0x00002000
37 37 #define FSL_DMA_MR_SAHE 0x00001000
  38 +
  39 +/*
  40 + * Bandwidth/pause control determines how many bytes a given
  41 + * channel is allowed to transfer before the DMA engine pauses
  42 + * the current channel and switches to the next channel
  43 + */
  44 +#define FSL_DMA_MR_BWC 0x08000000
38 45  
39 46 /* Special MR definition for MPC8349 */
40 47 #define FSL_DMA_MR_EOTIE 0x00000080