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Commit f679056b2fdd4e9b7c8eb42ba447cd9646236305

Authored by Gábor Stefanik
Committed by John W. Linville
1 parent 18889231e4

ssb: Implement the remaining rev.8 SPROM vars needed for LP-PHY 

Also add a "SPEX32" macro for extracting 32-bit SPROM variables.

Signed-off-by: Gábor Stefanik <netrolller.3d@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

Showing 3 changed files with 148 additions and 15 deletions Side-by-side Diff

... ... @@ -169,9 +169,15 @@
169 169 /* Get the word-offset for a SSB_SPROM_XXX define. */
170 170 #define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
171 171 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
172   -#define SPEX(_outvar, _offset, _mask, _shift) \
  172 +#define SPEX16(_outvar, _offset, _mask, _shift) \
173 173 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
  174 +#define SPEX32(_outvar, _offset, _mask, _shift) \
  175 + out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
  176 + in[SPOFF(_offset)]) & (_mask)) >> (_shift))
  177 +#define SPEX(_outvar, _offset, _mask, _shift) \
  178 + SPEX16(_outvar, _offset, _mask, _shift)
174 179  
  180 +
175 181 static inline u8 ssb_crc8(u8 crc, u8 data)
176 182 {
177 183 /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
... ... @@ -480,6 +486,8 @@
480 486 SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
481 487 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
482 488 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
  489 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
  490 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
483 491 SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
484 492 SSB_SPROM8_ANTAVAIL_A_SHIFT);
485 493 SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
486 494  
... ... @@ -490,12 +498,55 @@
490 498 SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
491 499 SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
492 500 SSB_SPROM8_ITSSI_A_SHIFT);
  501 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
  502 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
  503 + SSB_SPROM8_MAXP_AL_SHIFT);
493 504 SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
494 505 SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
495 506 SSB_SPROM8_GPIOA_P1_SHIFT);
496 507 SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
497 508 SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
498 509 SSB_SPROM8_GPIOB_P3_SHIFT);
  510 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
  511 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
  512 + SSB_SPROM8_TRI5G_SHIFT);
  513 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
  514 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
  515 + SSB_SPROM8_TRI5GH_SHIFT);
  516 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
  517 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
  518 + SSB_SPROM8_RXPO5G_SHIFT);
  519 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
  520 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
  521 + SSB_SPROM8_RSSISMC2G_SHIFT);
  522 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
  523 + SSB_SPROM8_RSSISAV2G_SHIFT);
  524 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
  525 + SSB_SPROM8_BXA2G_SHIFT);
  526 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
  527 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
  528 + SSB_SPROM8_RSSISMC5G_SHIFT);
  529 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
  530 + SSB_SPROM8_RSSISAV5G_SHIFT);
  531 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
  532 + SSB_SPROM8_BXA5G_SHIFT);
  533 + SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
  534 + SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
  535 + SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
  536 + SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
  537 + SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
  538 + SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
  539 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
  540 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
  541 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
  542 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
  543 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
  544 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
  545 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
  546 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
  547 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
  548 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
  549 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
499 550  
500 551 /* Extract the antenna gain values. */
501 552 SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
include/linux/ssb/ssb.h
Diff comments   View file @ f679056
... ... @@ -27,24 +27,54 @@
27 27 u8 et1mdcport; /* MDIO for enet1 */
28 28 u8 board_rev; /* Board revision number from SPROM. */
29 29 u8 country_code; /* Country Code */
30   - u8 ant_available_a; /* A-PHY antenna available bits (up to 4) */
31   - u8 ant_available_bg; /* B/G-PHY antenna available bits (up to 4) */
  30 + u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
  31 + u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
32 32 u16 pa0b0;
33 33 u16 pa0b1;
34 34 u16 pa0b2;
35 35 u16 pa1b0;
36 36 u16 pa1b1;
37 37 u16 pa1b2;
  38 + u16 pa1lob0;
  39 + u16 pa1lob1;
  40 + u16 pa1lob2;
  41 + u16 pa1hib0;
  42 + u16 pa1hib1;
  43 + u16 pa1hib2;
38 44 u8 gpio0; /* GPIO pin 0 */
39 45 u8 gpio1; /* GPIO pin 1 */
40 46 u8 gpio2; /* GPIO pin 2 */
41 47 u8 gpio3; /* GPIO pin 3 */
42   - u16 maxpwr_a; /* A-PHY Amplifier Max Power (in dBm Q5.2) */
43   - u16 maxpwr_bg; /* B/G-PHY Amplifier Max Power (in dBm Q5.2) */
  48 + u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
  49 + u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
  50 + u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
  51 + u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
44 52 u8 itssi_a; /* Idle TSSI Target for A-PHY */
45 53 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
46   - u16 boardflags_lo; /* Boardflags (low 16 bits) */
47   - u16 boardflags_hi; /* Boardflags (high 16 bits) */
  54 + u8 tri2g; /* 2.4GHz TX isolation */
  55 + u8 tri5gl; /* 5.2GHz TX isolation */
  56 + u8 tri5g; /* 5.3GHz TX isolation */
  57 + u8 tri5gh; /* 5.8GHz TX isolation */
  58 + u8 rxpo2g; /* 2GHz RX power offset */
  59 + u8 rxpo5g; /* 5GHz RX power offset */
  60 + u8 rssisav2g; /* 2GHz RSSI params */
  61 + u8 rssismc2g;
  62 + u8 rssismf2g;
  63 + u8 bxa2g; /* 2GHz BX arch */
  64 + u8 rssisav5g; /* 5GHz RSSI params */
  65 + u8 rssismc5g;
  66 + u8 rssismf5g;
  67 + u8 bxa5g; /* 5GHz BX arch */
  68 + u16 cck2gpo; /* CCK power offset */
  69 + u32 ofdm2gpo; /* 2.4GHz OFDM power offset */
  70 + u32 ofdm5glpo; /* 5.2GHz OFDM power offset */
  71 + u32 ofdm5gpo; /* 5.3GHz OFDM power offset */
  72 + u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */
  73 + u16 boardflags_lo; /* Board flags (bits 0-15) */
  74 + u16 boardflags_hi; /* Board flags (bits 16-31) */
  75 + u16 boardflags2_lo; /* Board flags (bits 32-47) */
  76 + u16 boardflags2_hi; /* Board flags (bits 48-63) */
  77 + /* TODO store board flags in a single u64 */
48 78  
49 79 /* Antenna gain values for up to 4 antennas
50 80 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
... ... @@ -58,7 +88,7 @@
58 88 } ghz5; /* 5GHz band */
59 89 } antenna_gain;
60 90  
61   - /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */
  91 + /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
62 92 };
63 93  
64 94 /* Information about the PCB the circuitry is soldered on. */
include/linux/ssb/ssb_regs.h
Diff comments   View file @ f679056
... ... @@ -162,7 +162,7 @@
162 162  
163 163 /* SPROM shadow area. If not otherwise noted, fields are
164 164 * two bytes wide. Note that the SPROM can _only_ be read
165   - * in two-byte quantinies.
  165 + * in two-byte quantities.
166 166 */
167 167 #define SSB_SPROMSIZE_WORDS 64
168 168 #define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
... ... @@ -327,8 +327,11 @@
327 327 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
328 328  
329 329 /* SPROM Revision 8 */
330   -#define SSB_SPROM8_BFLLO 0x1084 /* Boardflags (low 16 bits) */
331   -#define SSB_SPROM8_BFLHI 0x1086 /* Boardflags Hi */
  330 +#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
  331 +#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
  332 +#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
  333 +#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
  334 +#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
332 335 #define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
333 336 #define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
334 337 #define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
335 338  
336 339  
... ... @@ -354,14 +357,63 @@
354 357 #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
355 358 #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
356 359 #define SSB_SPROM8_GPIOB_P3_SHIFT 8
357   -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power BG in path 1 */
358   -#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
  360 +#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
  361 +#define SSB_SPROM8_RSSISMF2G 0x000F
  362 +#define SSB_SPROM8_RSSISMC2G 0x00F0
  363 +#define SSB_SPROM8_RSSISMC2G_SHIFT 4
  364 +#define SSB_SPROM8_RSSISAV2G 0x0700
  365 +#define SSB_SPROM8_RSSISAV2G_SHIFT 8
  366 +#define SSB_SPROM8_BXA2G 0x1800
  367 +#define SSB_SPROM8_BXA2G_SHIFT 11
  368 +#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
  369 +#define SSB_SPROM8_RSSISMF5G 0x000F
  370 +#define SSB_SPROM8_RSSISMC5G 0x00F0
  371 +#define SSB_SPROM8_RSSISMC5G_SHIFT 4
  372 +#define SSB_SPROM8_RSSISAV5G 0x0700
  373 +#define SSB_SPROM8_RSSISAV5G_SHIFT 8
  374 +#define SSB_SPROM8_BXA5G 0x1800
  375 +#define SSB_SPROM8_BXA5G_SHIFT 11
  376 +#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
  377 +#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
  378 +#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
  379 +#define SSB_SPROM8_TRI5G_SHIFT 8
  380 +#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
  381 +#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
  382 +#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
  383 +#define SSB_SPROM8_TRI5GH_SHIFT 8
  384 +#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
  385 +#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
  386 +#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
  387 +#define SSB_SPROM8_RXPO5G_SHIFT 8
  388 +#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
  389 +#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
359 390 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
360 391 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
361   -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power A in path 1 */
362   -#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
  392 +#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
  393 +#define SSB_SPROM8_PA0B1 0x10C4
  394 +#define SSB_SPROM8_PA0B2 0x10C6
  395 +#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
  396 +#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
363 397 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
364 398 #define SSB_SPROM8_ITSSI_A_SHIFT 8
  399 +#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
  400 +#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
  401 +#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
  402 +#define SSB_SPROM8_MAXP_AL_SHIFT 8
  403 +#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
  404 +#define SSB_SPROM8_PA1B1 0x10CE
  405 +#define SSB_SPROM8_PA1B2 0x10D0
  406 +#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
  407 +#define SSB_SPROM8_PA1LOB1 0x10D4
  408 +#define SSB_SPROM8_PA1LOB2 0x10D6
  409 +#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
  410 +#define SSB_SPROM8_PA1HIB1 0x10DA
  411 +#define SSB_SPROM8_PA1HIB2 0x10DC
  412 +#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
  413 +#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
  414 +#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
  415 +#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
  416 +#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
365 417  
366 418 /* Values for SSB_SPROM1_BINF_CCODE */
367 419 enum {