Merge branch 'for-2.6.38' into for-2.6.39

Mark Brown
2 parents 905f6952c5 3017358a75
Showing 4 changed files Side-by-side Diff
include/sound/wm8903.h
sound/soc/codecs/wm8903.c
sound/soc/codecs/wm8994.c
sound/soc/soc-dapm.c
@@ -17,13 +17,9 @@
 /*
  * R6 (0x06) - Mic Bias Control 0
  */
-#define WM8903_MICDET_HYST_ENA                  0x0080  /* MICDET_HYST_ENA */
-#define WM8903_MICDET_HYST_ENA_MASK             0x0080  /* MICDET_HYST_ENA */
-#define WM8903_MICDET_HYST_ENA_SHIFT                 7  /* MICDET_HYST_ENA */
-#define WM8903_MICDET_HYST_ENA_WIDTH                 1  /* MICDET_HYST_ENA */
-#define WM8903_MICDET_THR_MASK                  0x0070  /* MICDET_THR - [6:4] */
-#define WM8903_MICDET_THR_SHIFT                      4  /* MICDET_THR - [6:4] */
-#define WM8903_MICDET_THR_WIDTH                      3  /* MICDET_THR - [6:4] */
+#define WM8903_MICDET_THR_MASK                  0x0030  /* MICDET_THR - [5:4] */
+#define WM8903_MICDET_THR_SHIFT                      4  /* MICDET_THR - [5:4] */
+#define WM8903_MICDET_THR_WIDTH                      2  /* MICDET_THR - [5:4] */
 #define WM8903_MICSHORT_THR_MASK                0x000C  /* MICSHORT_THR - [3:2] */
 #define WM8903_MICSHORT_THR_SHIFT                    2  /* MICSHORT_THR - [3:2] */
 #define WM8903_MICSHORT_THR_WIDTH                    2  /* MICSHORT_THR - [3:2] */
@@ -1620,7 +1620,7 @@
 			    WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
 			    irq_mask);
  
-	if (det && shrt) {
+	if (det || shrt) {
 		/* Enable mic detection, this may not have been set through
 		 * platform data (eg, if the defaults are OK). */
 		snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
@@ -107,6 +107,9 @@
  
 	int revision;
 	struct wm8994_pdata *pdata;
+
+	unsigned int aif1clk_enable:1;
+	unsigned int aif2clk_enable:1;
 };
  
 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
@@ -1004,6 +1007,93 @@
 	}
 }
  
+static int late_enable_ev(struct snd_soc_dapm_widget *w,
+			  struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_codec *codec = w->codec;
+	struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		if (wm8994->aif1clk_enable)
+			snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
+					    WM8994_AIF1CLK_ENA_MASK,
+					    WM8994_AIF1CLK_ENA);
+		if (wm8994->aif2clk_enable)
+			snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
+					    WM8994_AIF2CLK_ENA_MASK,
+					    WM8994_AIF2CLK_ENA);
+		break;
+	}
+
+	return 0;
+}
+
+static int late_disable_ev(struct snd_soc_dapm_widget *w,
+			   struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_codec *codec = w->codec;
+	struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+	switch (event) {
+	case SND_SOC_DAPM_POST_PMD:
+		if (wm8994->aif1clk_enable) {
+			snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
+					    WM8994_AIF1CLK_ENA_MASK, 0);
+			wm8994->aif1clk_enable = 0;
+		}
+		if (wm8994->aif2clk_enable) {
+			snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
+					    WM8994_AIF2CLK_ENA_MASK, 0);
+			wm8994->aif2clk_enable = 0;
+		}
+		break;
+	}
+
+	return 0;
+}
+
+static int aif1clk_ev(struct snd_soc_dapm_widget *w,
+		      struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_codec *codec = w->codec;
+	struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wm8994->aif1clk_enable = 1;
+		break;
+	}
+
+	return 0;
+}
+
+static int aif2clk_ev(struct snd_soc_dapm_widget *w,
+		      struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_codec *codec = w->codec;
+	struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wm8994->aif2clk_enable = 1;
+		break;
+	}
+
+	return 0;
+}
+
+static int dac_ev(struct snd_soc_dapm_widget *w,
+		  struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_codec *codec = w->codec;
+	unsigned int mask = 1 << w->shift;
+
+	snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
+			    mask, mask);
+	return 0;
+}
+
 static const char *hp_mux_text[] = {
 	"Mixer",
 	"DAC",
@@ -1272,6 +1362,47 @@
 static const struct snd_kcontrol_new aif2dacr_src_mux =
 	SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
  
+static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
+SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
+	SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
+	SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+	late_enable_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+	late_enable_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+	late_enable_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+	late_enable_ev, SND_SOC_DAPM_PRE_PMU),
+
+SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
+};
+
+static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
+SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
+};
+
+static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
+SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
+	dac_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
+	dac_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
+	dac_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
+	dac_ev, SND_SOC_DAPM_PRE_PMU),
+};
+
+static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
+SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
+SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
+SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
+SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
+};
+
 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
 SND_SOC_DAPM_INPUT("DMIC1DAT"),
 SND_SOC_DAPM_INPUT("DMIC2DAT"),
@@ -1284,9 +1415,6 @@
 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
  
-SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
-SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
-
 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
 		     0, WM8994_POWER_MANAGEMENT_4, 9, 0),
 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
@@ -1372,11 +1500,6 @@
 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
  
-SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
-SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
-SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
-SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
-
 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
  
  
@@ -1516,14 +1639,12 @@
 	{ "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
  
 	/* DAC1 inputs */
-	{ "DAC1L", NULL, "DAC1L Mixer" },
 	{ "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
 	{ "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
 	{ "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
 	{ "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
 	{ "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  
-	{ "DAC1R", NULL, "DAC1R Mixer" },
 	{ "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
 	{ "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
 	{ "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
@@ -1532,7 +1653,6 @@
  
 	/* DAC2/AIF2 outputs  */
 	{ "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
-	{ "DAC2L", NULL, "AIF2DAC2L Mixer" },
 	{ "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
 	{ "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
 	{ "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
@@ -1540,7 +1660,6 @@
 	{ "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  
 	{ "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
-	{ "DAC2R", NULL, "AIF2DAC2R Mixer" },
 	{ "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
 	{ "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
 	{ "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
@@ -1584,6 +1703,24 @@
 	{ "Right Headphone Mux", "DAC", "DAC1R" },
 };
  
+static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
+	{ "DAC1L", NULL, "Late DAC1L Enable PGA" },
+	{ "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
+	{ "DAC1R", NULL, "Late DAC1R Enable PGA" },
+	{ "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
+	{ "DAC2L", NULL, "Late DAC2L Enable PGA" },
+	{ "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
+	{ "DAC2R", NULL, "Late DAC2R Enable PGA" },
+	{ "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
+};
+
+static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
+	{ "DAC1L", NULL, "DAC1L Mixer" },
+	{ "DAC1R", NULL, "DAC1R Mixer" },
+	{ "DAC2L", NULL, "AIF2DAC2L Mixer" },
+	{ "DAC2R", NULL, "AIF2DAC2R Mixer" },
+};
+
 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
 	{ "AIF1DACDAT", NULL, "AIF2DACDAT" },
 	{ "AIF2DACDAT", NULL, "AIF1DACDAT" },
  
@@ -2514,7 +2651,23 @@
 {
 	struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 	int i, ret;
+	unsigned int val, mask;
  
+	if (wm8994->revision < 4) {
+		/* force a HW read */
+		val = wm8994_reg_read(codec->control_data,
+				      WM8994_POWER_MANAGEMENT_5);
+
+		/* modify the cache only */
+		codec->cache_only = 1;
+		mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
+			WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
+		val &= mask;
+		snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
+				    mask, val);
+		codec->cache_only = 0;
+	}
+
 	/* Restore the registers */
 	ret = snd_soc_cache_sync(codec);
 	if (ret != 0)
@@ -3125,6 +3278,17 @@
 	case WM8994:
 		snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
 					  ARRAY_SIZE(wm8994_specific_dapm_widgets));
+		if (wm8994->revision < 4) {
+			snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
+						  ARRAY_SIZE(wm8994_lateclk_revd_widgets));
+			snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
+						  ARRAY_SIZE(wm8994_dac_revd_widgets));
+		} else {
+			snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
+						  ARRAY_SIZE(wm8994_lateclk_widgets));
+			snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
+						  ARRAY_SIZE(wm8994_dac_widgets));
+		}
 		break;
 	case WM8958:
 		snd_soc_add_controls(codec, wm8958_snd_controls,
  
@@ -3143,10 +3307,15 @@
 		snd_soc_dapm_add_routes(dapm, wm8994_intercon,
 					ARRAY_SIZE(wm8994_intercon));
  
-		if (wm8994->revision < 4)
+		if (wm8994->revision < 4) {
 			snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
 						ARRAY_SIZE(wm8994_revd_intercon));
-			
+			snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
+						ARRAY_SIZE(wm8994_lateclk_revd_intercon));
+		} else {
+			snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
+						ARRAY_SIZE(wm8994_lateclk_intercon));
+		}
 		break;
 	case WM8958:
 		snd_soc_dapm_add_routes(dapm, wm8958_intercon,
@@ -712,7 +712,15 @@
 		    !path->connected(path->source, path->sink))
 			continue;
  
-		if (path->sink && path->sink->power_check &&
+		if (!path->sink)
+			continue;
+
+		if (path->sink->force) {
+			power = 1;
+			break;
+		}
+
+		if (path->sink->power_check &&
 		    path->sink->power_check(path->sink)) {
 			power = 1;
 			break;
...	...	@@ -17,13 +17,9 @@
17	17	/*
18	18	* R6 (0x06) - Mic Bias Control 0
19	19	*/
20		-#define WM8903_MICDET_HYST_ENA 0x0080 /* MICDET_HYST_ENA */
21		-#define WM8903_MICDET_HYST_ENA_MASK 0x0080 /* MICDET_HYST_ENA */
22		-#define WM8903_MICDET_HYST_ENA_SHIFT 7 /* MICDET_HYST_ENA */
23		-#define WM8903_MICDET_HYST_ENA_WIDTH 1 /* MICDET_HYST_ENA */
24		-#define WM8903_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */
25		-#define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */
26		-#define WM8903_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */
	20	+#define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
	21	+#define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [5:4] */
	22	+#define WM8903_MICDET_THR_WIDTH 2 /* MICDET_THR - [5:4] */
27	23	#define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
28	24	#define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */
29	25	#define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */
...	...	@@ -1620,7 +1620,7 @@
1620	1620	WM8903_MICDET_EINT \| WM8903_MICSHRT_EINT,
1621	1621	irq_mask);
1622	1622
1623		- if (det && shrt) {
	1623	+ if (det \|\| shrt) {
1624	1624	/* Enable mic detection, this may not have been set through
1625	1625	* platform data (eg, if the defaults are OK). */
1626	1626	snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
...	...	@@ -107,6 +107,9 @@
107	107
108	108	int revision;
109	109	struct wm8994_pdata *pdata;
	110	+
	111	+ unsigned int aif1clk_enable:1;
	112	+ unsigned int aif2clk_enable:1;
110	113	};
111	114
112	115	static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
...	...	@@ -1004,6 +1007,93 @@
1004	1007	}
1005	1008	}
1006	1009
	1010	+static int late_enable_ev(struct snd_soc_dapm_widget *w,
	1011	+ struct snd_kcontrol *kcontrol, int event)
	1012	+{
	1013	+ struct snd_soc_codec *codec = w->codec;
	1014	+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
	1015	+
	1016	+ switch (event) {
	1017	+ case SND_SOC_DAPM_PRE_PMU:
	1018	+ if (wm8994->aif1clk_enable)
	1019	+ snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
	1020	+ WM8994_AIF1CLK_ENA_MASK,
	1021	+ WM8994_AIF1CLK_ENA);
	1022	+ if (wm8994->aif2clk_enable)
	1023	+ snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
	1024	+ WM8994_AIF2CLK_ENA_MASK,
	1025	+ WM8994_AIF2CLK_ENA);
	1026	+ break;
	1027	+ }
	1028	+
	1029	+ return 0;
	1030	+}
	1031	+
	1032	+static int late_disable_ev(struct snd_soc_dapm_widget *w,
	1033	+ struct snd_kcontrol *kcontrol, int event)
	1034	+{
	1035	+ struct snd_soc_codec *codec = w->codec;
	1036	+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
	1037	+
	1038	+ switch (event) {
	1039	+ case SND_SOC_DAPM_POST_PMD:
	1040	+ if (wm8994->aif1clk_enable) {
	1041	+ snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
	1042	+ WM8994_AIF1CLK_ENA_MASK, 0);
	1043	+ wm8994->aif1clk_enable = 0;
	1044	+ }
	1045	+ if (wm8994->aif2clk_enable) {
	1046	+ snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
	1047	+ WM8994_AIF2CLK_ENA_MASK, 0);
	1048	+ wm8994->aif2clk_enable = 0;
	1049	+ }
	1050	+ break;
	1051	+ }
	1052	+
	1053	+ return 0;
	1054	+}
	1055	+
	1056	+static int aif1clk_ev(struct snd_soc_dapm_widget *w,
	1057	+ struct snd_kcontrol *kcontrol, int event)
	1058	+{
	1059	+ struct snd_soc_codec *codec = w->codec;
	1060	+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
	1061	+
	1062	+ switch (event) {
	1063	+ case SND_SOC_DAPM_PRE_PMU:
	1064	+ wm8994->aif1clk_enable = 1;
	1065	+ break;
	1066	+ }
	1067	+
	1068	+ return 0;
	1069	+}
	1070	+
	1071	+static int aif2clk_ev(struct snd_soc_dapm_widget *w,
	1072	+ struct snd_kcontrol *kcontrol, int event)
	1073	+{
	1074	+ struct snd_soc_codec *codec = w->codec;
	1075	+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
	1076	+
	1077	+ switch (event) {
	1078	+ case SND_SOC_DAPM_PRE_PMU:
	1079	+ wm8994->aif2clk_enable = 1;
	1080	+ break;
	1081	+ }
	1082	+
	1083	+ return 0;
	1084	+}
	1085	+
	1086	+static int dac_ev(struct snd_soc_dapm_widget *w,
	1087	+ struct snd_kcontrol *kcontrol, int event)
	1088	+{
	1089	+ struct snd_soc_codec *codec = w->codec;
	1090	+ unsigned int mask = 1 << w->shift;
	1091	+
	1092	+ snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
	1093	+ mask, mask);
	1094	+ return 0;
	1095	+}
	1096	+
1007	1097	static const char *hp_mux_text[] = {
1008	1098	"Mixer",
1009	1099	"DAC",
...	...	@@ -1272,6 +1362,47 @@
1272	1362	static const struct snd_kcontrol_new aif2dacr_src_mux =
1273	1363	SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1274	1364
	1365	+static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
	1366	+SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
	1367	+ SND_SOC_DAPM_PRE_PMU \| SND_SOC_DAPM_POST_PMD),
	1368	+SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
	1369	+ SND_SOC_DAPM_PRE_PMU \| SND_SOC_DAPM_POST_PMD),
	1370	+
	1371	+SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
	1372	+ late_enable_ev, SND_SOC_DAPM_PRE_PMU),
	1373	+SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
	1374	+ late_enable_ev, SND_SOC_DAPM_PRE_PMU),
	1375	+SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
	1376	+ late_enable_ev, SND_SOC_DAPM_PRE_PMU),
	1377	+SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
	1378	+ late_enable_ev, SND_SOC_DAPM_PRE_PMU),
	1379	+
	1380	+SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
	1381	+};
	1382	+
	1383	+static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
	1384	+SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
	1385	+SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
	1386	+};
	1387	+
	1388	+static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
	1389	+SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
	1390	+ dac_ev, SND_SOC_DAPM_PRE_PMU),
	1391	+SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
	1392	+ dac_ev, SND_SOC_DAPM_PRE_PMU),
	1393	+SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
	1394	+ dac_ev, SND_SOC_DAPM_PRE_PMU),
	1395	+SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
	1396	+ dac_ev, SND_SOC_DAPM_PRE_PMU),
	1397	+};
	1398	+
	1399	+static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
	1400	+SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
	1401	+SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
	1402	+SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
	1403	+SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
	1404	+};
	1405	+
1275	1406	static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1276	1407	SND_SOC_DAPM_INPUT("DMIC1DAT"),
1277	1408	SND_SOC_DAPM_INPUT("DMIC2DAT"),
...	...	@@ -1284,9 +1415,6 @@
1284	1415	SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1285	1416	SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1286	1417
1287		-SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1288		-SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1289		-
1290	1418	SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1291	1419	0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1292	1420	SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
...	...	@@ -1372,11 +1500,6 @@
1372	1500	SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1373	1501	SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1374	1502
1375		-SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1376		-SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1377		-SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1378		-SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1379		-
1380	1503	SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1381	1504	SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1382	1505
1383	1506
...	...	@@ -1516,14 +1639,12 @@
1516	1639	{ "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1517	1640
1518	1641	/* DAC1 inputs */
1519		- { "DAC1L", NULL, "DAC1L Mixer" },
1520	1642	{ "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1521	1643	{ "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1522	1644	{ "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1523	1645	{ "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1524	1646	{ "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1525	1647
1526		- { "DAC1R", NULL, "DAC1R Mixer" },
1527	1648	{ "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1528	1649	{ "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1529	1650	{ "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
...	...	@@ -1532,7 +1653,6 @@
1532	1653
1533	1654	/* DAC2/AIF2 outputs */
1534	1655	{ "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1535		- { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1536	1656	{ "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1537	1657	{ "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1538	1658	{ "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
...	...	@@ -1540,7 +1660,6 @@
1540	1660	{ "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1541	1661
1542	1662	{ "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1543		- { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1544	1663	{ "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1545	1664	{ "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1546	1665	{ "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
...	...	@@ -1584,6 +1703,24 @@
1584	1703	{ "Right Headphone Mux", "DAC", "DAC1R" },
1585	1704	};
1586	1705
	1706	+static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
	1707	+ { "DAC1L", NULL, "Late DAC1L Enable PGA" },
	1708	+ { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
	1709	+ { "DAC1R", NULL, "Late DAC1R Enable PGA" },
	1710	+ { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
	1711	+ { "DAC2L", NULL, "Late DAC2L Enable PGA" },
	1712	+ { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
	1713	+ { "DAC2R", NULL, "Late DAC2R Enable PGA" },
	1714	+ { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
	1715	+};
	1716	+
	1717	+static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
	1718	+ { "DAC1L", NULL, "DAC1L Mixer" },
	1719	+ { "DAC1R", NULL, "DAC1R Mixer" },
	1720	+ { "DAC2L", NULL, "AIF2DAC2L Mixer" },
	1721	+ { "DAC2R", NULL, "AIF2DAC2R Mixer" },
	1722	+};
	1723	+
1587	1724	static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1588	1725	{ "AIF1DACDAT", NULL, "AIF2DACDAT" },
1589	1726	{ "AIF2DACDAT", NULL, "AIF1DACDAT" },
1590	1727
...	...	@@ -2514,7 +2651,23 @@
2514	2651	{
2515	2652	struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2516	2653	int i, ret;
	2654	+ unsigned int val, mask;
2517	2655
	2656	+ if (wm8994->revision < 4) {
	2657	+ /* force a HW read */
	2658	+ val = wm8994_reg_read(codec->control_data,
	2659	+ WM8994_POWER_MANAGEMENT_5);
	2660	+
	2661	+ /* modify the cache only */
	2662	+ codec->cache_only = 1;
	2663	+ mask = WM8994_DAC1R_ENA \| WM8994_DAC1L_ENA \|
	2664	+ WM8994_DAC2R_ENA \| WM8994_DAC2L_ENA;
	2665	+ val &= mask;
	2666	+ snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
	2667	+ mask, val);
	2668	+ codec->cache_only = 0;
	2669	+ }
	2670	+
2518	2671	/* Restore the registers */
2519	2672	ret = snd_soc_cache_sync(codec);
2520	2673	if (ret != 0)
...	...	@@ -3125,6 +3278,17 @@
3125	3278	case WM8994:
3126	3279	snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3127	3280	ARRAY_SIZE(wm8994_specific_dapm_widgets));
	3281	+ if (wm8994->revision < 4) {
	3282	+ snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
	3283	+ ARRAY_SIZE(wm8994_lateclk_revd_widgets));
	3284	+ snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
	3285	+ ARRAY_SIZE(wm8994_dac_revd_widgets));
	3286	+ } else {
	3287	+ snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
	3288	+ ARRAY_SIZE(wm8994_lateclk_widgets));
	3289	+ snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
	3290	+ ARRAY_SIZE(wm8994_dac_widgets));
	3291	+ }
3128	3292	break;
3129	3293	case WM8958:
3130	3294	snd_soc_add_controls(codec, wm8958_snd_controls,
3131	3295
...	...	@@ -3143,10 +3307,15 @@
3143	3307	snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3144	3308	ARRAY_SIZE(wm8994_intercon));
3145	3309
3146		- if (wm8994->revision < 4)
	3310	+ if (wm8994->revision < 4) {
3147	3311	snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3148	3312	ARRAY_SIZE(wm8994_revd_intercon));
3149		-
	3313	+ snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
	3314	+ ARRAY_SIZE(wm8994_lateclk_revd_intercon));
	3315	+ } else {
	3316	+ snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
	3317	+ ARRAY_SIZE(wm8994_lateclk_intercon));
	3318	+ }
3150	3319	break;
3151	3320	case WM8958:
3152	3321	snd_soc_dapm_add_routes(dapm, wm8958_intercon,
...	...	@@ -712,7 +712,15 @@
712	712	!path->connected(path->source, path->sink))
713	713	continue;
714	714
715		- if (path->sink && path->sink->power_check &&
	715	+ if (!path->sink)
	716	+ continue;
	717	+
	718	+ if (path->sink->force) {
	719	+ power = 1;
	720	+ break;
	721	+ }
	722	+
	723	+ if (path->sink->power_check &&
716	724	path->sink->power_check(path->sink)) {
717	725	power = 1;
718	726	break;