crypto: qat - introduce chip info structure

Introduce the chip info structure which contains device specific information. The initialization path has been split between common and hardware specific in order to facilitate the introduction of the next generation hardware. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

crypto: qat - introduce chip info structure
Introduce the chip info structure which contains device specific information. The initialization path has been split between common and hardware specific in order to facilitate the introduction of the next generation hardware. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Jack Xu · Herbert Xu
1 parent 58c173b9cb
Showing 3 changed files with 88 additions and 35 deletions Side-by-side Diff
drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h
drivers/crypto/qat/qat_common/qat_hal.c
drivers/crypto/qat/qat_common/qat_uclo.c
@@ -22,13 +22,18 @@
 	unsigned int max_ustore;
 };
  
+struct icp_qat_fw_loader_chip_info {
+	bool sram_visible;
+	bool fw_auth;
+};
+
 struct icp_qat_fw_loader_handle {
 	struct icp_qat_fw_loader_hal_handle *hal_handle;
+	struct icp_qat_fw_loader_chip_info *chip_info;
 	struct pci_dev *pci_dev;
 	void *obj_handle;
 	void *sobj_handle;
 	void *mobj_handle;
-	bool fw_auth;
 	void __iomem *hal_sram_addr_v;
 	void __iomem *hal_cap_g_ctl_csr_addr_v;
 	void __iomem *hal_cap_ae_xfer_csr_addr_v;
@@ -646,23 +646,41 @@
 	return 0;
 }
  
-int qat_hal_init(struct adf_accel_dev *accel_dev)
+static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
+			     struct adf_accel_dev *accel_dev)
 {
-	unsigned char ae;
-	unsigned int max_en_ae_id = 0;
-	struct icp_qat_fw_loader_handle *handle;
 	struct adf_accel_pci *pci_info = &accel_dev->accel_pci_dev;
 	struct adf_hw_device_data *hw_data = accel_dev->hw_device;
 	struct adf_bar *misc_bar =
 			&pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)];
-	unsigned long ae_mask = hw_data->ae_mask;
-	unsigned int csr_val = 0;
+	unsigned int max_en_ae_id = 0;
 	struct adf_bar *sram_bar;
+	unsigned int csr_val = 0;
+	unsigned long ae_mask;
+	unsigned char ae = 0;
+	int ret = 0;
  
-	handle = kzalloc(sizeof(*handle), GFP_KERNEL);
-	if (!handle)
-		return -ENOMEM;
+	handle->pci_dev = pci_info->pci_dev;
+	switch (handle->pci_dev->device) {
+	case PCI_DEVICE_ID_INTEL_QAT_C62X:
+	case PCI_DEVICE_ID_INTEL_QAT_C3XXX:
+		handle->chip_info->sram_visible = false;
+		handle->chip_info->fw_auth = true;
+		break;
+	case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
+		handle->chip_info->sram_visible = true;
+		handle->chip_info->fw_auth = false;
+		break;
+	default:
+		ret = -EINVAL;
+		goto out_err;
+	}
  
+	if (handle->chip_info->sram_visible) {
+		sram_bar =
+			&pci_info->pci_bars[hw_data->get_sram_bar_id(hw_data)];
+		handle->hal_sram_addr_v = sram_bar->virt_addr;
+	}
 	handle->hal_cap_g_ctl_csr_addr_v =
 		(void __iomem *)((uintptr_t)misc_bar->virt_addr +
 				 ICP_QAT_CAP_OFFSET);
  
@@ -676,22 +694,14 @@
 		(void __iomem *)((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v +
 				 LOCAL_TO_XFER_REG_OFFSET);
 	handle->pci_dev = pci_info->pci_dev;
-	if (handle->pci_dev->device == PCI_DEVICE_ID_INTEL_QAT_DH895XCC) {
-		sram_bar =
-			&pci_info->pci_bars[hw_data->get_sram_bar_id(hw_data)];
-		handle->hal_sram_addr_v = sram_bar->virt_addr;
-	}
-	handle->fw_auth = (handle->pci_dev->device ==
-			   PCI_DEVICE_ID_INTEL_QAT_DH895XCC) ? false : true;
-	handle->hal_handle = kzalloc(sizeof(*handle->hal_handle), GFP_KERNEL);
-	if (!handle->hal_handle)
-		goto out_hal_handle;
 	handle->hal_handle->revision_id = accel_dev->accel_pci_dev.revid;
 	handle->hal_handle->ae_mask = hw_data->ae_mask;
 	handle->hal_handle->slice_mask = hw_data->accel_mask;
 	/* create AE objects */
 	handle->hal_handle->upc_mask = 0x1ffff;
 	handle->hal_handle->max_ustore = 0x4000;
+
+	ae_mask = handle->hal_handle->ae_mask;
 	for_each_set_bit(ae, &ae_mask, ICP_QAT_UCLO_MAX_AE) {
 		handle->hal_handle->aes[ae].free_addr = 0;
 		handle->hal_handle->aes[ae].free_size =
  
  
  
  
  
  
  
@@ -703,37 +713,75 @@
 		max_en_ae_id = ae;
 	}
 	handle->hal_handle->ae_max_num = max_en_ae_id + 1;
+
+	/* Set SIGNATURE_ENABLE[0] to 0x1 in order to enable ALU_OUT csr */
+	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
+		csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE);
+		csr_val |= 0x1;
+		qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val);
+	}
+out_err:
+	return ret;
+}
+
+int qat_hal_init(struct adf_accel_dev *accel_dev)
+{
+	struct icp_qat_fw_loader_handle *handle;
+	int ret = 0;
+
+	handle = kzalloc(sizeof(*handle), GFP_KERNEL);
+	if (!handle)
+		return -ENOMEM;
+
+	handle->hal_handle = kzalloc(sizeof(*handle->hal_handle), GFP_KERNEL);
+	if (!handle->hal_handle) {
+		ret = -ENOMEM;
+		goto out_hal_handle;
+	}
+
+	handle->chip_info = kzalloc(sizeof(*handle->chip_info), GFP_KERNEL);
+	if (!handle->chip_info) {
+		ret = -ENOMEM;
+		goto out_chip_info;
+	}
+
+	ret = qat_hal_chip_init(handle, accel_dev);
+	if (ret) {
+		dev_err(&GET_DEV(accel_dev), "qat_hal_chip_init error\n");
+		goto out_err;
+	}
+
 	/* take all AEs out of reset */
-	if (qat_hal_clr_reset(handle)) {
+	ret = qat_hal_clr_reset(handle);
+	if (ret) {
 		dev_err(&GET_DEV(accel_dev), "qat_hal_clr_reset error\n");
 		goto out_err;
 	}
+
 	qat_hal_clear_xfer(handle);
-	if (!handle->fw_auth) {
-		if (qat_hal_clear_gpr(handle))
+	if (!handle->chip_info->fw_auth) {
+		ret = qat_hal_clear_gpr(handle);
+		if (ret)
 			goto out_err;
 	}
  
-	/* Set SIGNATURE_ENABLE[0] to 0x1 in order to enable ALU_OUT csr */
-	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
-		csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE);
-		csr_val |= 0x1;
-		qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val);
-	}
 	accel_dev->fw_loader->fw_loader = handle;
 	return 0;
  
 out_err:
+	kfree(handle->chip_info);
+out_chip_info:
 	kfree(handle->hal_handle);
 out_hal_handle:
 	kfree(handle);
-	return -EFAULT;
+	return ret;
 }
  
 void qat_hal_deinit(struct icp_qat_fw_loader_handle *handle)
 {
 	if (!handle)
 		return;
+	kfree(handle->chip_info);
 	kfree(handle->hal_handle);
 	kfree(handle);
 }
@@ -746,7 +794,7 @@
 	u32 ae_ctr = 0;
 	int retry = 0;
  
-	if (handle->fw_auth) {
+	if (handle->chip_info->fw_auth) {
 		ae_ctr = hweight32(ae_mask);
 		SET_CAP_CSR(handle, FCU_CONTROL, FCU_CTRL_CMD_START);
 		do {
@@ -770,7 +818,7 @@
 void qat_hal_stop(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
 		  unsigned int ctx_mask)
 {
-	if (!handle->fw_auth)
+	if (!handle->chip_info->fw_auth)
 		qat_hal_disable_ctx(handle, ae, ctx_mask);
 }
  
@@ -1405,7 +1405,7 @@
 	struct icp_qat_fw_auth_desc *desc = NULL;
 	int status = 0;
  
-	if (handle->fw_auth) {
+	if (handle->chip_info->fw_auth) {
 		if (!qat_uclo_map_auth_fw(handle, addr_ptr, mem_size, &desc))
 			status = qat_uclo_auth_fw(handle, desc);
 		qat_uclo_ummap_auth_fw(handle, &desc);
@@ -1718,7 +1718,7 @@
 		obj_size = mem_size;
 	}
  
-	return (handle->fw_auth) ?
+	return (handle->chip_info->fw_auth) ?
 			qat_uclo_map_suof_obj(handle, obj_addr, obj_size) :
 			qat_uclo_map_uof_obj(handle, obj_addr, obj_size);
 }
@@ -1909,7 +1909,7 @@
  
 int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle)
 {
-	return (handle->fw_auth) ? qat_uclo_wr_suof_img(handle) :
+	return (handle->chip_info->fw_auth) ? qat_uclo_wr_suof_img(handle) :
 				   qat_uclo_wr_uof_img(handle);
 }
...	...	@@ -22,13 +22,18 @@
22	22	unsigned int max_ustore;
23	23	};
24	24
	25	+struct icp_qat_fw_loader_chip_info {
	26	+ bool sram_visible;
	27	+ bool fw_auth;
	28	+};
	29	+
25	30	struct icp_qat_fw_loader_handle {
26	31	struct icp_qat_fw_loader_hal_handle *hal_handle;
	32	+ struct icp_qat_fw_loader_chip_info *chip_info;
27	33	struct pci_dev *pci_dev;
28	34	void *obj_handle;
29	35	void *sobj_handle;
30	36	void *mobj_handle;
31		- bool fw_auth;
32	37	void __iomem *hal_sram_addr_v;
33	38	void __iomem *hal_cap_g_ctl_csr_addr_v;
34	39	void __iomem *hal_cap_ae_xfer_csr_addr_v;
...	...	@@ -646,23 +646,41 @@
646	646	return 0;
647	647	}
648	648
649		-int qat_hal_init(struct adf_accel_dev *accel_dev)
	649	+static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
	650	+ struct adf_accel_dev *accel_dev)
650	651	{
651		- unsigned char ae;
652		- unsigned int max_en_ae_id = 0;
653		- struct icp_qat_fw_loader_handle *handle;
654	652	struct adf_accel_pci *pci_info = &accel_dev->accel_pci_dev;
655	653	struct adf_hw_device_data *hw_data = accel_dev->hw_device;
656	654	struct adf_bar *misc_bar =
657	655	&pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)];
658		- unsigned long ae_mask = hw_data->ae_mask;
659		- unsigned int csr_val = 0;
	656	+ unsigned int max_en_ae_id = 0;
660	657	struct adf_bar *sram_bar;
	658	+ unsigned int csr_val = 0;
	659	+ unsigned long ae_mask;
	660	+ unsigned char ae = 0;
	661	+ int ret = 0;
661	662
662		- handle = kzalloc(sizeof(*handle), GFP_KERNEL);
663		- if (!handle)
664		- return -ENOMEM;
	663	+ handle->pci_dev = pci_info->pci_dev;
	664	+ switch (handle->pci_dev->device) {
	665	+ case PCI_DEVICE_ID_INTEL_QAT_C62X:
	666	+ case PCI_DEVICE_ID_INTEL_QAT_C3XXX:
	667	+ handle->chip_info->sram_visible = false;
	668	+ handle->chip_info->fw_auth = true;
	669	+ break;
	670	+ case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
	671	+ handle->chip_info->sram_visible = true;
	672	+ handle->chip_info->fw_auth = false;
	673	+ break;
	674	+ default:
	675	+ ret = -EINVAL;
	676	+ goto out_err;
	677	+ }
665	678
	679	+ if (handle->chip_info->sram_visible) {
	680	+ sram_bar =
	681	+ &pci_info->pci_bars[hw_data->get_sram_bar_id(hw_data)];
	682	+ handle->hal_sram_addr_v = sram_bar->virt_addr;
	683	+ }
666	684	handle->hal_cap_g_ctl_csr_addr_v =
667	685	(void __iomem *)((uintptr_t)misc_bar->virt_addr +
668	686	ICP_QAT_CAP_OFFSET);
669	687
...	...	@@ -676,22 +694,14 @@
676	694	(void __iomem *)((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v +
677	695	LOCAL_TO_XFER_REG_OFFSET);
678	696	handle->pci_dev = pci_info->pci_dev;
679		- if (handle->pci_dev->device == PCI_DEVICE_ID_INTEL_QAT_DH895XCC) {
680		- sram_bar =
681		- &pci_info->pci_bars[hw_data->get_sram_bar_id(hw_data)];
682		- handle->hal_sram_addr_v = sram_bar->virt_addr;
683		- }
684		- handle->fw_auth = (handle->pci_dev->device ==
685		- PCI_DEVICE_ID_INTEL_QAT_DH895XCC) ? false : true;
686		- handle->hal_handle = kzalloc(sizeof(*handle->hal_handle), GFP_KERNEL);
687		- if (!handle->hal_handle)
688		- goto out_hal_handle;
689	697	handle->hal_handle->revision_id = accel_dev->accel_pci_dev.revid;
690	698	handle->hal_handle->ae_mask = hw_data->ae_mask;
691	699	handle->hal_handle->slice_mask = hw_data->accel_mask;
692	700	/* create AE objects */
693	701	handle->hal_handle->upc_mask = 0x1ffff;
694	702	handle->hal_handle->max_ustore = 0x4000;
	703	+
	704	+ ae_mask = handle->hal_handle->ae_mask;
695	705	for_each_set_bit(ae, &ae_mask, ICP_QAT_UCLO_MAX_AE) {
696	706	handle->hal_handle->aes[ae].free_addr = 0;
697	707	handle->hal_handle->aes[ae].free_size =
698	708
699	709
700	710
701	711
702	712
703	713
704	714
...	...	@@ -703,37 +713,75 @@
703	713	max_en_ae_id = ae;
704	714	}
705	715	handle->hal_handle->ae_max_num = max_en_ae_id + 1;
	716	+
	717	+ /* Set SIGNATURE_ENABLE[0] to 0x1 in order to enable ALU_OUT csr */
	718	+ for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
	719	+ csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE);
	720	+ csr_val \|= 0x1;
	721	+ qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val);
	722	+ }
	723	+out_err:
	724	+ return ret;
	725	+}
	726	+
	727	+int qat_hal_init(struct adf_accel_dev *accel_dev)
	728	+{
	729	+ struct icp_qat_fw_loader_handle *handle;
	730	+ int ret = 0;
	731	+
	732	+ handle = kzalloc(sizeof(*handle), GFP_KERNEL);
	733	+ if (!handle)
	734	+ return -ENOMEM;
	735	+
	736	+ handle->hal_handle = kzalloc(sizeof(*handle->hal_handle), GFP_KERNEL);
	737	+ if (!handle->hal_handle) {
	738	+ ret = -ENOMEM;
	739	+ goto out_hal_handle;
	740	+ }
	741	+
	742	+ handle->chip_info = kzalloc(sizeof(*handle->chip_info), GFP_KERNEL);
	743	+ if (!handle->chip_info) {
	744	+ ret = -ENOMEM;
	745	+ goto out_chip_info;
	746	+ }
	747	+
	748	+ ret = qat_hal_chip_init(handle, accel_dev);
	749	+ if (ret) {
	750	+ dev_err(&GET_DEV(accel_dev), "qat_hal_chip_init error\n");
	751	+ goto out_err;
	752	+ }
	753	+
706	754	/* take all AEs out of reset */
707		- if (qat_hal_clr_reset(handle)) {
	755	+ ret = qat_hal_clr_reset(handle);
	756	+ if (ret) {
708	757	dev_err(&GET_DEV(accel_dev), "qat_hal_clr_reset error\n");
709	758	goto out_err;
710	759	}
	760	+
711	761	qat_hal_clear_xfer(handle);
712		- if (!handle->fw_auth) {
713		- if (qat_hal_clear_gpr(handle))
	762	+ if (!handle->chip_info->fw_auth) {
	763	+ ret = qat_hal_clear_gpr(handle);
	764	+ if (ret)
714	765	goto out_err;
715	766	}
716	767
717		- /* Set SIGNATURE_ENABLE[0] to 0x1 in order to enable ALU_OUT csr */
718		- for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
719		- csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE);
720		- csr_val \|= 0x1;
721		- qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val);
722		- }
723	768	accel_dev->fw_loader->fw_loader = handle;
724	769	return 0;
725	770
726	771	out_err:
	772	+ kfree(handle->chip_info);
	773	+out_chip_info:
727	774	kfree(handle->hal_handle);
728	775	out_hal_handle:
729	776	kfree(handle);
730		- return -EFAULT;
	777	+ return ret;
731	778	}
732	779
733	780	void qat_hal_deinit(struct icp_qat_fw_loader_handle *handle)
734	781	{
735	782	if (!handle)
736	783	return;
	784	+ kfree(handle->chip_info);
737	785	kfree(handle->hal_handle);
738	786	kfree(handle);
739	787	}
...	...	@@ -746,7 +794,7 @@
746	794	u32 ae_ctr = 0;
747	795	int retry = 0;
748	796
749		- if (handle->fw_auth) {
	797	+ if (handle->chip_info->fw_auth) {
750	798	ae_ctr = hweight32(ae_mask);
751	799	SET_CAP_CSR(handle, FCU_CONTROL, FCU_CTRL_CMD_START);
752	800	do {
...	...	@@ -770,7 +818,7 @@
770	818	void qat_hal_stop(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
771	819	unsigned int ctx_mask)
772	820	{
773		- if (!handle->fw_auth)
	821	+ if (!handle->chip_info->fw_auth)
774	822	qat_hal_disable_ctx(handle, ae, ctx_mask);
775	823	}
776	824
...	...	@@ -1405,7 +1405,7 @@
1405	1405	struct icp_qat_fw_auth_desc *desc = NULL;
1406	1406	int status = 0;
1407	1407
1408		- if (handle->fw_auth) {
	1408	+ if (handle->chip_info->fw_auth) {
1409	1409	if (!qat_uclo_map_auth_fw(handle, addr_ptr, mem_size, &desc))
1410	1410	status = qat_uclo_auth_fw(handle, desc);
1411	1411	qat_uclo_ummap_auth_fw(handle, &desc);
...	...	@@ -1718,7 +1718,7 @@
1718	1718	obj_size = mem_size;
1719	1719	}
1720	1720
1721		- return (handle->fw_auth) ?
	1721	+ return (handle->chip_info->fw_auth) ?
1722	1722	qat_uclo_map_suof_obj(handle, obj_addr, obj_size) :
1723	1723	qat_uclo_map_uof_obj(handle, obj_addr, obj_size);
1724	1724	}
...	...	@@ -1909,7 +1909,7 @@
1909	1909
1910	1910	int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle)
1911	1911	{
1912		- return (handle->fw_auth) ? qat_uclo_wr_suof_img(handle) :
	1912	+ return (handle->chip_info->fw_auth) ? qat_uclo_wr_suof_img(handle) :
1913	1913	qat_uclo_wr_uof_img(handle);
1914	1914	}