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Commit ff20775d189cf8f36684c88f6f95e00d21bc783c

Authored by Olof Johansson
2 parents 39aa437e18 c99cd90d98

Merge tag 'renesas-marzen-board-removal-for-v4.3' of git://git.kernel.org/pub/sc… 

…m/linux/kernel/git/horms/renesas into next/cleanup

Renesas ARM Based SoC Marzen Board Removal for v4.3

* Remove legacy r8a7779 SoC code
* Remove legacy marzen board code

* tag 'renesas-marzen-board-removal-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7779: Remove legacy SoC code
  ARM: shmobile: marzen: Remove legacy board code
  ARM: shmobile: r8a7779: Cleanup header file
  ARM: shmobile: marzen-reference: Remove C board code
  ARM: shmobile: r8a7779: Generic SMP ops
  ARM: shmobile: r8a7779: Generic CCF and timer support

Signed-off-by: Olof Johansson <olof@lixom.net>

Showing 10 changed files Side-by-side Diff

arch/arm/boot/dts/Makefile
Diff comments   View file @ ff20775
... ... @@ -503,7 +503,8 @@
503 503 dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
504 504 r8a7778-bockw.dtb \
505 505 r8a7778-bockw-reference.dtb \
506   - r8a7779-marzen.dtb
  506 + r8a7779-marzen.dtb \
  507 + sh73a0-kzm9g.dtb
507 508 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
508 509 emev2-kzm9d.dtb \
509 510 r7s72100-genmai.dtb \
arch/arm/mach-shmobile/Kconfig
Diff comments   View file @ ff20775
... ... @@ -89,13 +89,6 @@
89 89 select ARCH_RMOBILE
90 90 select RENESAS_INTC_IRQPIN
91 91  
92   -comment "Renesas ARM SoCs Board Type"
93   -
94   -config MACH_MARZEN
95   - bool "MARZEN board"
96   - depends on ARCH_R8A7779
97   - select REGULATOR_FIXED_VOLTAGE if REGULATOR
98   -
99 92 comment "Renesas ARM SoCs System Configuration"
100 93 endif
101 94  
... ... @@ -138,13 +131,6 @@
138 131 of not supporting a number of devices.
139 132  
140 133 This is intended to aid developers
141   -
142   -config MACH_MARZEN
143   - bool "MARZEN board"
144   - depends on ARCH_R8A7779
145   - select ARCH_REQUIRE_GPIOLIB
146   - select REGULATOR_FIXED_VOLTAGE if REGULATOR
147   - select USE_OF
148 134  
149 135 comment "Renesas ARM SoCs System Configuration"
150 136  
arch/arm/mach-shmobile/Makefile
Diff comments   View file @ ff20775
... ... @@ -21,7 +21,6 @@
21 21 ifndef CONFIG_COMMON_CLK
22 22 obj-y += clock.o
23 23 obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
24   -obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
25 24 endif
26 25  
27 26 # CPU reset vector handling objects
28 27  
... ... @@ -49,13 +48,9 @@
49 48 obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o
50 49  
51 50 # Board objects
52   -ifdef CONFIG_ARCH_SHMOBILE_MULTI
53   -obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o
54   -else
  51 +ifndef CONFIG_ARCH_SHMOBILE_MULTI
55 52 obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
56 53 obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
57   -obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
58   -endif
59 54  
60 55 # Framework support
61 56 obj-$(CONFIG_SMP) += $(smp-y)
arch/arm/mach-shmobile/Makefile.boot
Diff comments   View file @ ff20775
... ... @@ -2,7 +2,6 @@
2 2 loadaddr-y :=
3 3 loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
4 4 loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
5   -loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
6 5  
7 6 __ZRELADDR := $(sort $(loadaddr-y))
8 7 zreladdr-y += $(__ZRELADDR)
arch/arm/mach-shmobile/board-marzen-reference.c
View file @ ff20775
1   -/*
2   - * marzen board support - Reference DT implementation
3   - *
4   - * Copyright (C) 2011 Renesas Solutions Corp.
5   - * Copyright (C) 2011 Magnus Damm
6   - * Copyright (C) 2013 Simon Horman
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License as published by
10   - * the Free Software Foundation; version 2 of the License.
11   - *
12   - * This program is distributed in the hope that it will be useful,
13   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15   - * GNU General Public License for more details.
16   - */
17   -
18   -#include <linux/clk/shmobile.h>
19   -#include <linux/clocksource.h>
20   -#include <linux/of_platform.h>
21   -
22   -#include <asm/irq.h>
23   -#include <asm/mach/arch.h>
24   -
25   -#include "common.h"
26   -#include "irqs.h"
27   -#include "r8a7779.h"
28   -
29   -static void __init marzen_init_timer(void)
30   -{
31   - r8a7779_clocks_init(r8a7779_read_mode_pins());
32   - clocksource_of_init();
33   -}
34   -
35   -static void __init marzen_init(void)
36   -{
37   - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
38   - r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
39   -}
40   -
41   -static const char *const marzen_boards_compat_dt[] __initconst = {
42   - "renesas,marzen",
43   - "renesas,marzen-reference",
44   - NULL,
45   -};
46   -
47   -DT_MACHINE_START(MARZEN, "marzen")
48   - .smp = smp_ops(r8a7779_smp_ops),
49   - .map_io = r8a7779_map_io,
50   - .init_early = shmobile_init_delay,
51   - .init_time = marzen_init_timer,
52   - .init_irq = r8a7779_init_irq_dt,
53   - .init_machine = marzen_init,
54   - .init_late = shmobile_init_late,
55   - .dt_compat = marzen_boards_compat_dt,
56   -MACHINE_END
arch/arm/mach-shmobile/board-marzen.c
View file @ ff20775
1   -/*
2   - * marzen board support
3   - *
4   - * Copyright (C) 2011, 2013 Renesas Solutions Corp.
5   - * Copyright (C) 2011 Magnus Damm
6   - * Copyright (C) 2013 Cogent Embedded, Inc.
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License as published by
10   - * the Free Software Foundation; version 2 of the License.
11   - *
12   - * This program is distributed in the hope that it will be useful,
13   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15   - * GNU General Public License for more details.
16   - */
17   -
18   -#include <linux/kernel.h>
19   -#include <linux/init.h>
20   -#include <linux/interrupt.h>
21   -#include <linux/irq.h>
22   -#include <linux/platform_device.h>
23   -#include <linux/delay.h>
24   -#include <linux/io.h>
25   -#include <linux/leds.h>
26   -#include <linux/dma-mapping.h>
27   -#include <linux/pinctrl/machine.h>
28   -#include <linux/platform_data/camera-rcar.h>
29   -#include <linux/platform_data/gpio-rcar.h>
30   -#include <linux/platform_data/usb-rcar-phy.h>
31   -#include <linux/regulator/fixed.h>
32   -#include <linux/regulator/machine.h>
33   -#include <linux/smsc911x.h>
34   -#include <linux/spi/spi.h>
35   -#include <linux/spi/sh_hspi.h>
36   -#include <linux/mmc/host.h>
37   -#include <linux/mmc/sh_mobile_sdhi.h>
38   -#include <linux/mfd/tmio.h>
39   -
40   -#include <media/soc_camera.h>
41   -#include <asm/mach-types.h>
42   -#include <asm/mach/arch.h>
43   -#include <asm/traps.h>
44   -
45   -#include "common.h"
46   -#include "irqs.h"
47   -#include "r8a7779.h"
48   -
49   -/* Fixed 3.3V regulator to be used by SDHI0 */
50   -static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
51   - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
52   - REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
53   -};
54   -
55   -/* Dummy supplies, where voltage doesn't matter */
56   -static struct regulator_consumer_supply dummy_supplies[] = {
57   - REGULATOR_SUPPLY("vddvario", "smsc911x"),
58   - REGULATOR_SUPPLY("vdd33a", "smsc911x"),
59   -};
60   -
61   -/* USB PHY */
62   -static struct resource usb_phy_resources[] = {
63   - [0] = {
64   - .start = 0xffe70800,
65   - .end = 0xffe70900 - 1,
66   - .flags = IORESOURCE_MEM,
67   - },
68   -};
69   -
70   -static struct rcar_phy_platform_data usb_phy_platform_data;
71   -
72   -static struct platform_device usb_phy = {
73   - .name = "rcar_usb_phy",
74   - .id = -1,
75   - .dev = {
76   - .platform_data = &usb_phy_platform_data,
77   - },
78   - .resource = usb_phy_resources,
79   - .num_resources = ARRAY_SIZE(usb_phy_resources),
80   -};
81   -
82   -/* SMSC LAN89218 */
83   -static struct resource smsc911x_resources[] = {
84   - [0] = {
85   - .start = 0x18000000, /* ExCS0 */
86   - .end = 0x180000ff, /* A1->A7 */
87   - .flags = IORESOURCE_MEM,
88   - },
89   - [1] = {
90   - .start = irq_pin(1), /* IRQ 1 */
91   - .flags = IORESOURCE_IRQ,
92   - },
93   -};
94   -
95   -static struct smsc911x_platform_config smsc911x_platdata = {
96   - .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */
97   - .phy_interface = PHY_INTERFACE_MODE_MII,
98   - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
99   - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
100   -};
101   -
102   -static struct platform_device eth_device = {
103   - .name = "smsc911x",
104   - .id = -1,
105   - .dev = {
106   - .platform_data = &smsc911x_platdata,
107   - },
108   - .resource = smsc911x_resources,
109   - .num_resources = ARRAY_SIZE(smsc911x_resources),
110   -};
111   -
112   -static struct resource sdhi0_resources[] = {
113   - [0] = {
114   - .name = "sdhi0",
115   - .start = 0xffe4c000,
116   - .end = 0xffe4c0ff,
117   - .flags = IORESOURCE_MEM,
118   - },
119   - [1] = {
120   - .start = gic_iid(0x88),
121   - .flags = IORESOURCE_IRQ,
122   - },
123   -};
124   -
125   -static struct tmio_mmc_data sdhi0_platform_data = {
126   - .chan_priv_tx = (void *)HPBDMA_SLAVE_SDHI0_TX,
127   - .chan_priv_rx = (void *)HPBDMA_SLAVE_SDHI0_RX,
128   - .flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
129   - .capabilities = MMC_CAP_SD_HIGHSPEED,
130   -};
131   -
132   -static struct platform_device sdhi0_device = {
133   - .name = "sh_mobile_sdhi",
134   - .num_resources = ARRAY_SIZE(sdhi0_resources),
135   - .resource = sdhi0_resources,
136   - .id = 0,
137   - .dev = {
138   - .platform_data = &sdhi0_platform_data,
139   - }
140   -};
141   -
142   -/* Thermal */
143   -static struct resource thermal_resources[] = {
144   - [0] = {
145   - .start = 0xFFC48000,
146   - .end = 0xFFC48038 - 1,
147   - .flags = IORESOURCE_MEM,
148   - },
149   -};
150   -
151   -static struct platform_device thermal_device = {
152   - .name = "rcar_thermal",
153   - .resource = thermal_resources,
154   - .num_resources = ARRAY_SIZE(thermal_resources),
155   -};
156   -
157   -/* HSPI */
158   -static struct resource hspi_resources[] = {
159   - [0] = {
160   - .start = 0xFFFC7000,
161   - .end = 0xFFFC7018 - 1,
162   - .flags = IORESOURCE_MEM,
163   - },
164   -};
165   -
166   -static struct platform_device hspi_device = {
167   - .name = "sh-hspi",
168   - .id = 0,
169   - .resource = hspi_resources,
170   - .num_resources = ARRAY_SIZE(hspi_resources),
171   -};
172   -
173   -/* LEDS */
174   -static struct gpio_led marzen_leds[] = {
175   - {
176   - .name = "led2",
177   - .gpio = RCAR_GP_PIN(4, 29),
178   - .default_state = LEDS_GPIO_DEFSTATE_ON,
179   - }, {
180   - .name = "led3",
181   - .gpio = RCAR_GP_PIN(4, 30),
182   - .default_state = LEDS_GPIO_DEFSTATE_ON,
183   - }, {
184   - .name = "led4",
185   - .gpio = RCAR_GP_PIN(4, 31),
186   - .default_state = LEDS_GPIO_DEFSTATE_ON,
187   - },
188   -};
189   -
190   -static struct gpio_led_platform_data marzen_leds_pdata = {
191   - .leds = marzen_leds,
192   - .num_leds = ARRAY_SIZE(marzen_leds),
193   -};
194   -
195   -static struct platform_device leds_device = {
196   - .name = "leds-gpio",
197   - .id = 0,
198   - .dev = {
199   - .platform_data = &marzen_leds_pdata,
200   - },
201   -};
202   -
203   -/* VIN */
204   -static struct rcar_vin_platform_data vin_platform_data __initdata = {
205   - .flags = RCAR_VIN_BT656,
206   -};
207   -
208   -#define MARZEN_VIN(idx) \
209   -static struct resource vin##idx##_resources[] __initdata = { \
210   - DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \
211   - DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \
212   -}; \
213   - \
214   -static struct platform_device_info vin##idx##_info __initdata = { \
215   - .name = "r8a7779-vin", \
216   - .id = idx, \
217   - .res = vin##idx##_resources, \
218   - .num_res = ARRAY_SIZE(vin##idx##_resources), \
219   - .dma_mask = DMA_BIT_MASK(32), \
220   - .data = &vin_platform_data, \
221   - .size_data = sizeof(vin_platform_data), \
222   -}
223   -MARZEN_VIN(1);
224   -MARZEN_VIN(3);
225   -
226   -#define MARZEN_CAMERA(idx) \
227   -static struct i2c_board_info camera##idx##_info = { \
228   - I2C_BOARD_INFO("adv7180", 0x20 + (idx)), \
229   -}; \
230   - \
231   -static struct soc_camera_link iclink##idx##_adv7180 = { \
232   - .bus_id = 1 + 2 * (idx), \
233   - .i2c_adapter_id = 0, \
234   - .board_info = &camera##idx##_info, \
235   -}; \
236   - \
237   -static struct platform_device camera##idx##_device = { \
238   - .name = "soc-camera-pdrv", \
239   - .id = idx, \
240   - .dev = { \
241   - .platform_data = &iclink##idx##_adv7180, \
242   - }, \
243   -};
244   -
245   -MARZEN_CAMERA(0);
246   -MARZEN_CAMERA(1);
247   -
248   -static struct platform_device *marzen_devices[] __initdata = {
249   - &eth_device,
250   - &sdhi0_device,
251   - &thermal_device,
252   - &hspi_device,
253   - &leds_device,
254   - &usb_phy,
255   - &camera0_device,
256   - &camera1_device,
257   -};
258   -
259   -static const struct pinctrl_map marzen_pinctrl_map[] = {
260   - /* DU (CN10: ARGB0, CN13: LVDS) */
261   - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779",
262   - "du0_rgb888", "du0"),
263   - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779",
264   - "du0_sync_1", "du0"),
265   - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779",
266   - "du0_clk_out_0", "du0"),
267   - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779",
268   - "du1_rgb666", "du1"),
269   - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779",
270   - "du1_sync_1", "du1"),
271   - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779",
272   - "du1_clk_out", "du1"),
273   - /* HSPI0 */
274   - PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
275   - "hspi0", "hspi0"),
276   - /* SCIF2 (CN18: DEBUG0) */
277   - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
278   - "scif2_data_c", "scif2"),
279   - /* SCIF4 (CN19: DEBUG1) */
280   - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
281   - "scif4_data", "scif4"),
282   - /* SDHI0 */
283   - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
284   - "sdhi0_data4", "sdhi0"),
285   - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
286   - "sdhi0_ctrl", "sdhi0"),
287   - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
288   - "sdhi0_cd", "sdhi0"),
289   - /* SMSC */
290   - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
291   - "intc_irq1_b", "intc"),
292   - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
293   - "lbsc_ex_cs0", "lbsc"),
294   - /* USB0 */
295   - PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
296   - "usb0", "usb0"),
297   - /* USB1 */
298   - PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
299   - "usb1", "usb1"),
300   - /* USB2 */
301   - PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779",
302   - "usb2", "usb2"),
303   - /* VIN1 */
304   - PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779",
305   - "vin1_clk", "vin1"),
306   - PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779",
307   - "vin1_data8", "vin1"),
308   - /* VIN3 */
309   - PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779",
310   - "vin3_clk", "vin3"),
311   - PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779",
312   - "vin3_data8", "vin3"),
313   -};
314   -
315   -static void __init marzen_init(void)
316   -{
317   - regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
318   - ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
319   - regulator_register_fixed(1, dummy_supplies,
320   - ARRAY_SIZE(dummy_supplies));
321   -
322   - pinctrl_register_mappings(marzen_pinctrl_map,
323   - ARRAY_SIZE(marzen_pinctrl_map));
324   - r8a7779_pinmux_init();
325   - r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */
326   -
327   - r8a7779_add_standard_devices();
328   - platform_device_register_full(&vin1_info);
329   - platform_device_register_full(&vin3_info);
330   - platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
331   -}
332   -
333   -static const char *const marzen_boards_compat_dt[] __initconst = {
334   - "renesas,marzen",
335   - NULL,
336   -};
337   -
338   -DT_MACHINE_START(MARZEN, "marzen")
339   - .smp = smp_ops(r8a7779_smp_ops),
340   - .map_io = r8a7779_map_io,
341   - .init_early = r8a7779_add_early_devices,
342   - .init_irq = r8a7779_init_irq_dt,
343   - .init_machine = marzen_init,
344   - .init_late = r8a7779_init_late,
345   - .dt_compat = marzen_boards_compat_dt,
346   - .init_time = r8a7779_earlytimer_init,
347   -MACHINE_END
arch/arm/mach-shmobile/clock-r8a7779.c
View file @ ff20775
1   -/*
2   - * r8a7779 clock framework support
3   - *
4   - * Copyright (C) 2011 Renesas Solutions Corp.
5   - * Copyright (C) 2011 Magnus Damm
6   - *
7   - * This program is free software; you can redistribute it and/or modify
8   - * it under the terms of the GNU General Public License as published by
9   - * the Free Software Foundation; either version 2 of the License
10   - *
11   - * This program is distributed in the hope that it will be useful,
12   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14   - * GNU General Public License for more details.
15   - */
16   -#include <linux/bitops.h>
17   -#include <linux/init.h>
18   -#include <linux/kernel.h>
19   -#include <linux/io.h>
20   -#include <linux/sh_clk.h>
21   -#include <linux/clkdev.h>
22   -#include <linux/sh_timer.h>
23   -
24   -#include "clock.h"
25   -#include "common.h"
26   -#include "r8a7779.h"
27   -
28   -/*
29   - * MD1 = 1 MD1 = 0
30   - * (PLLA = 1500) (PLLA = 1600)
31   - * (MHz) (MHz)
32   - *------------------------------------------------+--------------------
33   - * clkz 1000 (2/3) 800 (1/2)
34   - * clkzs 250 (1/6) 200 (1/8)
35   - * clki 750 (1/2) 800 (1/2)
36   - * clks 250 (1/6) 200 (1/8)
37   - * clks1 125 (1/12) 100 (1/16)
38   - * clks3 187.5 (1/8) 200 (1/8)
39   - * clks4 93.7 (1/16) 100 (1/16)
40   - * clkp 62.5 (1/24) 50 (1/32)
41   - * clkg 62.5 (1/24) 66.6 (1/24)
42   - * clkb, CLKOUT
43   - * (MD2 = 0) 62.5 (1/24) 66.6 (1/24)
44   - * (MD2 = 1) 41.6 (1/36) 50 (1/32)
45   -*/
46   -
47   -#define MD(nr) BIT(nr)
48   -
49   -#define MSTPCR0 IOMEM(0xffc80030)
50   -#define MSTPCR1 IOMEM(0xffc80034)
51   -#define MSTPCR3 IOMEM(0xffc8003c)
52   -#define MSTPSR1 IOMEM(0xffc80044)
53   -
54   -/* ioremap() through clock mapping mandatory to avoid
55   - * collision with ARM coherent DMA virtual memory range.
56   - */
57   -
58   -static struct clk_mapping cpg_mapping = {
59   - .phys = 0xffc80000,
60   - .len = 0x80,
61   -};
62   -
63   -/*
64   - * Default rate for the root input clock, reset this with clk_set_rate()
65   - * from the platform code.
66   - */
67   -static struct clk plla_clk = {
68   - /* .rate will be updated on r8a7779_clock_init() */
69   - .mapping = &cpg_mapping,
70   -};
71   -
72   -/*
73   - * clock ratio of these clock will be updated
74   - * on r8a7779_clock_init()
75   - */
76   -SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1);
77   -SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1);
78   -SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1);
79   -SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1);
80   -SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1);
81   -SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1);
82   -SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1);
83   -SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1);
84   -SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1);
85   -SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1);
86   -SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1);
87   -
88   -static struct clk *main_clks[] = {
89   - &plla_clk,
90   - &clkz_clk,
91   - &clkzs_clk,
92   - &clki_clk,
93   - &clks_clk,
94   - &clks1_clk,
95   - &clks3_clk,
96   - &clks4_clk,
97   - &clkb_clk,
98   - &clkout_clk,
99   - &clkp_clk,
100   - &clkg_clk,
101   -};
102   -
103   -enum { MSTP323, MSTP322, MSTP321, MSTP320,
104   - MSTP120,
105   - MSTP116, MSTP115, MSTP114,
106   - MSTP110, MSTP109, MSTP108,
107   - MSTP103, MSTP101, MSTP100,
108   - MSTP030,
109   - MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
110   - MSTP016, MSTP015, MSTP014,
111   - MSTP007,
112   - MSTP_NR };
113   -
114   -static struct clk mstp_clks[MSTP_NR] = {
115   - [MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */
116   - [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
117   - [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
118   - [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
119   - [MSTP120] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 20, MSTPSR1, 0), /* VIN3 */
120   - [MSTP116] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 16, MSTPSR1, 0), /* PCIe */
121   - [MSTP115] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 15, MSTPSR1, 0), /* SATA */
122   - [MSTP114] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 14, MSTPSR1, 0), /* Ether */
123   - [MSTP110] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 10, MSTPSR1, 0), /* VIN0 */
124   - [MSTP109] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 9, MSTPSR1, 0), /* VIN1 */
125   - [MSTP108] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 8, MSTPSR1, 0), /* VIN2 */
126   - [MSTP103] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 3, MSTPSR1, 0), /* DU */
127   - [MSTP101] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 1, MSTPSR1, 0), /* USB2 */
128   - [MSTP100] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 0, MSTPSR1, 0), /* USB0/1 */
129   - [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */
130   - [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */
131   - [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */
132   - [MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */
133   - [MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */
134   - [MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */
135   - [MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */
136   - [MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */
137   - [MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */
138   - [MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */
139   - [MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */
140   - [MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */
141   - [MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */
142   - [MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */
143   -};
144   -
145   -static struct clk_lookup lookups[] = {
146   - /* main clocks */
147   - CLKDEV_CON_ID("plla_clk", &plla_clk),
148   - CLKDEV_CON_ID("clkz_clk", &clkz_clk),
149   - CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
150   -
151   - /* DIV4 clocks */
152   - CLKDEV_CON_ID("shyway_clk", &clks_clk),
153   - CLKDEV_CON_ID("bus_clk", &clkout_clk),
154   - CLKDEV_CON_ID("shyway4_clk", &clks4_clk),
155   - CLKDEV_CON_ID("shyway3_clk", &clks3_clk),
156   - CLKDEV_CON_ID("shyway1_clk", &clks1_clk),
157   - CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
158   -
159   - /* MSTP32 clocks */
160   - CLKDEV_DEV_ID("r8a7779-vin.3", &mstp_clks[MSTP120]), /* VIN3 */
161   - CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
162   - CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
163   - CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
164   - CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
165   - CLKDEV_DEV_ID("r8a7779-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
166   - CLKDEV_DEV_ID("r8a7779-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
167   - CLKDEV_DEV_ID("r8a7779-vin.2", &mstp_clks[MSTP108]), /* VIN2 */
168   - CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
169   - CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
170   - CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
171   - CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
172   - CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]), /* TMU0 */
173   - CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
174   - CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
175   - CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
176   - CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
177   - CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
178   - CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
179   - CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
180   - CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
181   - CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
182   - CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
183   - CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
184   - CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
185   - CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
186   - CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
187   - CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
188   - CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
189   - CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
190   - CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
191   - CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
192   - CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
193   - CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
194   - CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
195   - CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
196   - CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
197   - CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
198   - CLKDEV_DEV_ID("ffe4e000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
199   - CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
200   - CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP320]), /* SDHI3 */
201   - CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
202   -};
203   -
204   -void __init r8a7779_clock_init(void)
205   -{
206   - u32 mode = r8a7779_read_mode_pins();
207   - int k, ret = 0;
208   -
209   - if (mode & MD(1)) {
210   - plla_clk.rate = 1500000000;
211   -
212   - SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3);
213   - SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6);
214   - SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
215   - SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6);
216   - SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12);
217   - SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
218   - SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
219   - SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24);
220   - SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
221   - if (mode & MD(2)) {
222   - SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36);
223   - SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36);
224   - } else {
225   - SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
226   - SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
227   - }
228   - } else {
229   - plla_clk.rate = 1600000000;
230   -
231   - SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2);
232   - SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8);
233   - SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
234   - SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8);
235   - SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16);
236   - SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
237   - SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
238   - SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32);
239   - SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
240   - if (mode & MD(2)) {
241   - SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32);
242   - SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32);
243   - } else {
244   - SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
245   - SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
246   - }
247   - }
248   -
249   - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
250   - ret = clk_register(main_clks[k]);
251   -
252   - if (!ret)
253   - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
254   -
255   - clkdev_add_table(lookups, ARRAY_SIZE(lookups));
256   -
257   - if (!ret)
258   - shmobile_clk_init();
259   - else
260   - panic("failed to setup r8a7779 clocks\n");
261   -}
262   -
263   -/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
264   -void __init __weak r8a7779_register_twd(void) { }
265   -
266   -void __init r8a7779_earlytimer_init(void)
267   -{
268   - r8a7779_clock_init();
269   - r8a7779_register_twd();
270   - shmobile_earlytimer_init();
271   -}
arch/arm/mach-shmobile/r8a7779.h
Diff comments   View file @ ff20775
... ... @@ -3,26 +3,7 @@
3 3  
4 4 #include <linux/sh_clk.h>
5 5  
6   -/* HPB-DMA slave IDs */
7   -enum {
8   - HPBDMA_SLAVE_DUMMY,
9   - HPBDMA_SLAVE_SDHI0_TX,
10   - HPBDMA_SLAVE_SDHI0_RX,
11   -};
12   -
13   -extern void r8a7779_init_irq_extpin(int irlm);
14   -extern void r8a7779_init_irq_extpin_dt(int irlm);
15   -extern void r8a7779_init_irq_dt(void);
16   -extern void r8a7779_map_io(void);
17   -extern void r8a7779_earlytimer_init(void);
18   -extern void r8a7779_add_early_devices(void);
19   -extern void r8a7779_add_standard_devices(void);
20   -extern void r8a7779_init_late(void);
21   -extern u32 r8a7779_read_mode_pins(void);
22   -extern void r8a7779_clock_init(void);
23   -extern void r8a7779_pinmux_init(void);
24 6 extern void r8a7779_pm_init(void);
25   -extern void r8a7779_register_twd(void);
26 7  
27 8 #ifdef CONFIG_PM
28 9 extern void __init r8a7779_init_pm_domains(void);
arch/arm/mach-shmobile/setup-r8a7779.c
Diff comments   View file @ ff20775
... ... @@ -14,37 +14,17 @@
14 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 15 * GNU General Public License for more details.
16 16 */
17   -#include <linux/kernel.h>
  17 +#include <linux/clk/shmobile.h>
  18 +#include <linux/clocksource.h>
18 19 #include <linux/init.h>
19   -#include <linux/interrupt.h>
20 20 #include <linux/irq.h>
21 21 #include <linux/irqchip.h>
22 22 #include <linux/irqchip/arm-gic.h>
23   -#include <linux/of_platform.h>
24   -#include <linux/platform_data/dma-rcar-hpbdma.h>
25   -#include <linux/platform_data/gpio-rcar.h>
26   -#include <linux/platform_data/irq-renesas-intc-irqpin.h>
27   -#include <linux/platform_device.h>
28   -#include <linux/delay.h>
29   -#include <linux/input.h>
30   -#include <linux/io.h>
31   -#include <linux/serial_sci.h>
32   -#include <linux/sh_timer.h>
33   -#include <linux/dma-mapping.h>
34   -#include <linux/usb/otg.h>
35   -#include <linux/usb/hcd.h>
36   -#include <linux/usb/ehci_pdriver.h>
37   -#include <linux/usb/ohci_pdriver.h>
38   -#include <linux/pm_runtime.h>
39 23  
40   -#include <asm/mach-types.h>
41 24 #include <asm/mach/arch.h>
42   -#include <asm/mach/time.h>
43 25 #include <asm/mach/map.h>
44   -#include <asm/hardware/cache-l2x0.h>
45 26  
46 27 #include "common.h"
47   -#include "irqs.h"
48 28 #include "r8a7779.h"
49 29  
50 30 static struct map_desc r8a7779_io_desc[] __initdata = {
... ... @@ -64,7 +44,7 @@
64 44 },
65 45 };
66 46  
67   -void __init r8a7779_map_io(void)
  47 +static void __init r8a7779_map_io(void)
68 48 {
69 49 debug_ll_io_init();
70 50 iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
71 51  
72 52  
73 53  
... ... @@ -80,652 +60,12 @@
80 60 #define INT2NTSR0 IOMEM(0xfe700060)
81 61 #define INT2NTSR1 IOMEM(0xfe700064)
82 62  
83   -static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
84   - .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
85   - .sense_bitfield_width = 2,
86   -};
87   -
88   -static struct resource irqpin0_resources[] __initdata = {
89   - DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
90   - DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
91   - DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
92   - DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
93   - DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
94   - DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
95   - DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
96   - DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
97   - DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
98   -};
99   -
100   -void __init r8a7779_init_irq_extpin_dt(int irlm)
  63 +static void __init r8a7779_init_irq_dt(void)
101 64 {
102   - void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
103   - u32 tmp;
104   -
105   - if (!icr0) {
106   - pr_warn("r8a7779: unable to setup external irq pin mode\n");
107   - return;
108   - }
109   -
110   - tmp = ioread32(icr0);
111   - if (irlm)
112   - tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
113   - else
114   - tmp &= ~(1 << 23); /* IRL mode - not supported */
115   - tmp |= (1 << 21); /* LVLMODE = 1 */
116   - iowrite32(tmp, icr0);
117   - iounmap(icr0);
118   -}
119   -
120   -void __init r8a7779_init_irq_extpin(int irlm)
121   -{
122   - r8a7779_init_irq_extpin_dt(irlm);
123   - if (irlm)
124   - platform_device_register_resndata(
125   - NULL, "renesas_intc_irqpin", -1,
126   - irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
127   - &irqpin0_platform_data, sizeof(irqpin0_platform_data));
128   -}
129   -
130   -/* PFC/GPIO */
131   -static struct resource r8a7779_pfc_resources[] = {
132   - DEFINE_RES_MEM(0xfffc0000, 0x023c),
133   -};
134   -
135   -static struct platform_device r8a7779_pfc_device = {
136   - .name = "pfc-r8a7779",
137   - .id = -1,
138   - .resource = r8a7779_pfc_resources,
139   - .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
140   -};
141   -
142   -#define R8A7779_GPIO(idx, npins) \
143   -static struct resource r8a7779_gpio##idx##_resources[] = { \
144   - DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \
145   - DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \
146   -}; \
147   - \
148   -static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
149   - .gpio_base = 32 * (idx), \
150   - .irq_base = 0, \
151   - .number_of_pins = npins, \
152   - .pctl_name = "pfc-r8a7779", \
153   -}; \
154   - \
155   -static struct platform_device r8a7779_gpio##idx##_device = { \
156   - .name = "gpio_rcar", \
157   - .id = idx, \
158   - .resource = r8a7779_gpio##idx##_resources, \
159   - .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
160   - .dev = { \
161   - .platform_data = &r8a7779_gpio##idx##_platform_data, \
162   - }, \
163   -}
164   -
165   -R8A7779_GPIO(0, 32);
166   -R8A7779_GPIO(1, 32);
167   -R8A7779_GPIO(2, 32);
168   -R8A7779_GPIO(3, 32);
169   -R8A7779_GPIO(4, 32);
170   -R8A7779_GPIO(5, 32);
171   -R8A7779_GPIO(6, 9);
172   -
173   -static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
174   - &r8a7779_pfc_device,
175   - &r8a7779_gpio0_device,
176   - &r8a7779_gpio1_device,
177   - &r8a7779_gpio2_device,
178   - &r8a7779_gpio3_device,
179   - &r8a7779_gpio4_device,
180   - &r8a7779_gpio5_device,
181   - &r8a7779_gpio6_device,
182   -};
183   -
184   -void __init r8a7779_pinmux_init(void)
185   -{
186   - platform_add_devices(r8a7779_pinctrl_devices,
187   - ARRAY_SIZE(r8a7779_pinctrl_devices));
188   -}
189   -
190   -/* SCIF */
191   -#define R8A7779_SCIF(index, baseaddr, irq) \
192   -static struct plat_sci_port scif##index##_platform_data = { \
193   - .type = PORT_SCIF, \
194   - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
195   - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
196   -}; \
197   - \
198   -static struct resource scif##index##_resources[] = { \
199   - DEFINE_RES_MEM(baseaddr, 0x100), \
200   - DEFINE_RES_IRQ(irq), \
201   -}; \
202   - \
203   -static struct platform_device scif##index##_device = { \
204   - .name = "sh-sci", \
205   - .id = index, \
206   - .resource = scif##index##_resources, \
207   - .num_resources = ARRAY_SIZE(scif##index##_resources), \
208   - .dev = { \
209   - .platform_data = &scif##index##_platform_data, \
210   - }, \
211   -}
212   -
213   -R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
214   -R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
215   -R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
216   -R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
217   -R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
218   -R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
219   -
220   -/* TMU */
221   -static struct sh_timer_config tmu0_platform_data = {
222   - .channels_mask = 7,
223   -};
224   -
225   -static struct resource tmu0_resources[] = {
226   - DEFINE_RES_MEM(0xffd80000, 0x30),
227   - DEFINE_RES_IRQ(gic_iid(0x40)),
228   - DEFINE_RES_IRQ(gic_iid(0x41)),
229   - DEFINE_RES_IRQ(gic_iid(0x42)),
230   -};
231   -
232   -static struct platform_device tmu0_device = {
233   - .name = "sh-tmu",
234   - .id = 0,
235   - .dev = {
236   - .platform_data = &tmu0_platform_data,
237   - },
238   - .resource = tmu0_resources,
239   - .num_resources = ARRAY_SIZE(tmu0_resources),
240   -};
241   -
242   -/* I2C */
243   -static struct resource rcar_i2c0_res[] = {
244   - {
245   - .start = 0xffc70000,
246   - .end = 0xffc70fff,
247   - .flags = IORESOURCE_MEM,
248   - }, {
249   - .start = gic_iid(0x6f),
250   - .flags = IORESOURCE_IRQ,
251   - },
252   -};
253   -
254   -static struct platform_device i2c0_device = {
255   - .name = "i2c-rcar",
256   - .id = 0,
257   - .resource = rcar_i2c0_res,
258   - .num_resources = ARRAY_SIZE(rcar_i2c0_res),
259   -};
260   -
261   -static struct resource rcar_i2c1_res[] = {
262   - {
263   - .start = 0xffc71000,
264   - .end = 0xffc71fff,
265   - .flags = IORESOURCE_MEM,
266   - }, {
267   - .start = gic_iid(0x72),
268   - .flags = IORESOURCE_IRQ,
269   - },
270   -};
271   -
272   -static struct platform_device i2c1_device = {
273   - .name = "i2c-rcar",
274   - .id = 1,
275   - .resource = rcar_i2c1_res,
276   - .num_resources = ARRAY_SIZE(rcar_i2c1_res),
277   -};
278   -
279   -static struct resource rcar_i2c2_res[] = {
280   - {
281   - .start = 0xffc72000,
282   - .end = 0xffc72fff,
283   - .flags = IORESOURCE_MEM,
284   - }, {
285   - .start = gic_iid(0x70),
286   - .flags = IORESOURCE_IRQ,
287   - },
288   -};
289   -
290   -static struct platform_device i2c2_device = {
291   - .name = "i2c-rcar",
292   - .id = 2,
293   - .resource = rcar_i2c2_res,
294   - .num_resources = ARRAY_SIZE(rcar_i2c2_res),
295   -};
296   -
297   -static struct resource rcar_i2c3_res[] = {
298   - {
299   - .start = 0xffc73000,
300   - .end = 0xffc73fff,
301   - .flags = IORESOURCE_MEM,
302   - }, {
303   - .start = gic_iid(0x71),
304   - .flags = IORESOURCE_IRQ,
305   - },
306   -};
307   -
308   -static struct platform_device i2c3_device = {
309   - .name = "i2c-rcar",
310   - .id = 3,
311   - .resource = rcar_i2c3_res,
312   - .num_resources = ARRAY_SIZE(rcar_i2c3_res),
313   -};
314   -
315   -static struct resource sata_resources[] = {
316   - [0] = {
317   - .name = "rcar-sata",
318   - .start = 0xfc600000,
319   - .end = 0xfc601fff,
320   - .flags = IORESOURCE_MEM,
321   - },
322   - [1] = {
323   - .start = gic_iid(0x84),
324   - .flags = IORESOURCE_IRQ,
325   - },
326   -};
327   -
328   -static struct platform_device sata_device = {
329   - .name = "sata_rcar",
330   - .id = -1,
331   - .resource = sata_resources,
332   - .num_resources = ARRAY_SIZE(sata_resources),
333   - .dev = {
334   - .dma_mask = &sata_device.dev.coherent_dma_mask,
335   - .coherent_dma_mask = DMA_BIT_MASK(32),
336   - },
337   -};
338   -
339   -/* USB */
340   -static struct usb_phy *phy;
341   -
342   -static int usb_power_on(struct platform_device *pdev)
343   -{
344   - if (IS_ERR(phy))
345   - return PTR_ERR(phy);
346   -
347   - pm_runtime_enable(&pdev->dev);
348   - pm_runtime_get_sync(&pdev->dev);
349   -
350   - usb_phy_init(phy);
351   -
352   - return 0;
353   -}
354   -
355   -static void usb_power_off(struct platform_device *pdev)
356   -{
357   - if (IS_ERR(phy))
358   - return;
359   -
360   - usb_phy_shutdown(phy);
361   -
362   - pm_runtime_put_sync(&pdev->dev);
363   - pm_runtime_disable(&pdev->dev);
364   -}
365   -
366   -static int ehci_init_internal_buffer(struct usb_hcd *hcd)
367   -{
368   - /*
369   - * Below are recommended values from the datasheet;
370   - * see [USB :: Setting of EHCI Internal Buffer].
371   - */
372   - /* EHCI IP internal buffer setting */
373   - iowrite32(0x00ff0040, hcd->regs + 0x0094);
374   - /* EHCI IP internal buffer enable */
375   - iowrite32(0x00000001, hcd->regs + 0x009C);
376   -
377   - return 0;
378   -}
379   -
380   -static struct usb_ehci_pdata ehcix_pdata = {
381   - .power_on = usb_power_on,
382   - .power_off = usb_power_off,
383   - .power_suspend = usb_power_off,
384   - .pre_setup = ehci_init_internal_buffer,
385   -};
386   -
387   -static struct resource ehci0_resources[] = {
388   - [0] = {
389   - .start = 0xffe70000,
390   - .end = 0xffe70400 - 1,
391   - .flags = IORESOURCE_MEM,
392   - },
393   - [1] = {
394   - .start = gic_iid(0x4c),
395   - .flags = IORESOURCE_IRQ,
396   - },
397   -};
398   -
399   -static struct platform_device ehci0_device = {
400   - .name = "ehci-platform",
401   - .id = 0,
402   - .dev = {
403   - .dma_mask = &ehci0_device.dev.coherent_dma_mask,
404   - .coherent_dma_mask = 0xffffffff,
405   - .platform_data = &ehcix_pdata,
406   - },
407   - .num_resources = ARRAY_SIZE(ehci0_resources),
408   - .resource = ehci0_resources,
409   -};
410   -
411   -static struct resource ehci1_resources[] = {
412   - [0] = {
413   - .start = 0xfff70000,
414   - .end = 0xfff70400 - 1,
415   - .flags = IORESOURCE_MEM,
416   - },
417   - [1] = {
418   - .start = gic_iid(0x4d),
419   - .flags = IORESOURCE_IRQ,
420   - },
421   -};
422   -
423   -static struct platform_device ehci1_device = {
424   - .name = "ehci-platform",
425   - .id = 1,
426   - .dev = {
427   - .dma_mask = &ehci1_device.dev.coherent_dma_mask,
428   - .coherent_dma_mask = 0xffffffff,
429   - .platform_data = &ehcix_pdata,
430   - },
431   - .num_resources = ARRAY_SIZE(ehci1_resources),
432   - .resource = ehci1_resources,
433   -};
434   -
435   -static struct usb_ohci_pdata ohcix_pdata = {
436   - .power_on = usb_power_on,
437   - .power_off = usb_power_off,
438   - .power_suspend = usb_power_off,
439   -};
440   -
441   -static struct resource ohci0_resources[] = {
442   - [0] = {
443   - .start = 0xffe70400,
444   - .end = 0xffe70800 - 1,
445   - .flags = IORESOURCE_MEM,
446   - },
447   - [1] = {
448   - .start = gic_iid(0x4c),
449   - .flags = IORESOURCE_IRQ,
450   - },
451   -};
452   -
453   -static struct platform_device ohci0_device = {
454   - .name = "ohci-platform",
455   - .id = 0,
456   - .dev = {
457   - .dma_mask = &ohci0_device.dev.coherent_dma_mask,
458   - .coherent_dma_mask = 0xffffffff,
459   - .platform_data = &ohcix_pdata,
460   - },
461   - .num_resources = ARRAY_SIZE(ohci0_resources),
462   - .resource = ohci0_resources,
463   -};
464   -
465   -static struct resource ohci1_resources[] = {
466   - [0] = {
467   - .start = 0xfff70400,
468   - .end = 0xfff70800 - 1,
469   - .flags = IORESOURCE_MEM,
470   - },
471   - [1] = {
472   - .start = gic_iid(0x4d),
473   - .flags = IORESOURCE_IRQ,
474   - },
475   -};
476   -
477   -static struct platform_device ohci1_device = {
478   - .name = "ohci-platform",
479   - .id = 1,
480   - .dev = {
481   - .dma_mask = &ohci1_device.dev.coherent_dma_mask,
482   - .coherent_dma_mask = 0xffffffff,
483   - .platform_data = &ohcix_pdata,
484   - },
485   - .num_resources = ARRAY_SIZE(ohci1_resources),
486   - .resource = ohci1_resources,
487   -};
488   -
489   -/* HPB-DMA */
490   -
491   -/* Asynchronous mode register bits */
492   -#define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */
493   -#define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */
494   -#define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */
495   -#define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */
496   -#define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */
497   -#define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */
498   -#define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */
499   -#define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */
500   -#define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */
501   -#define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */
502   -#define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */
503   -#define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */
504   -#define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */
505   -#define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */
506   -#define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */
507   -#define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */
508   -#define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */
509   -#define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */
510   -#define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */
511   -#define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */
512   -#define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */
513   -#define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */
514   -#define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */
515   -#define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */
516   -#define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */
517   -#define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */
518   -#define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */
519   -#define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */
520   -#define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */
521   -#define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */
522   -#define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */
523   -#define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */
524   -#define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */
525   -#define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */
526   -#define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */
527   -#define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */
528   -#define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */
529   -#define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */
530   -#define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */
531   -#define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */
532   -#define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */
533   -#define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */
534   -#define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */
535   -#define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */
536   -#define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */
537   -#define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */
538   -#define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */
539   -#define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */
540   -#define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */
541   -#define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */
542   -#define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */
543   -#define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */
544   -#define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */
545   -#define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */
546   -#define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */
547   -#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */
548   -#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
549   -#define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */
550   -#define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */
551   -#define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */
552   -#define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */
553   -#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */
554   -#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
555   -#define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */
556   -#define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */
557   -#define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */
558   -#define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */
559   -#define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */
560   -#define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */
561   -#define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */
562   -#define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */
563   -#define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */
564   -
565   -static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
566   - {
567   - .id = HPBDMA_SLAVE_SDHI0_TX,
568   - .addr = 0xffe4c000 + 0x30,
569   - .dcr = HPB_DMAE_DCR_SPDS_16BIT |
570   - HPB_DMAE_DCR_DMDL |
571   - HPB_DMAE_DCR_DPDS_16BIT,
572   - .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
573   - HPB_DMAE_ASYNCRSTR_ASRST22 |
574   - HPB_DMAE_ASYNCRSTR_ASRST23,
575   - .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
576   - HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
577   - .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
578   - HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
579   - .port = 0x0D0C,
580   - .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
581   - .dma_ch = 21,
582   - }, {
583   - .id = HPBDMA_SLAVE_SDHI0_RX,
584   - .addr = 0xffe4c000 + 0x30,
585   - .dcr = HPB_DMAE_DCR_SMDL |
586   - HPB_DMAE_DCR_SPDS_16BIT |
587   - HPB_DMAE_DCR_DPDS_16BIT,
588   - .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
589   - HPB_DMAE_ASYNCRSTR_ASRST22 |
590   - HPB_DMAE_ASYNCRSTR_ASRST23,
591   - .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
592   - HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
593   - .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
594   - HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
595   - .port = 0x0D0C,
596   - .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
597   - .dma_ch = 22,
598   - },
599   -};
600   -
601   -static const struct hpb_dmae_channel hpb_dmae_channels[] = {
602   - HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
603   - HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
604   -};
605   -
606   -static struct hpb_dmae_pdata dma_platform_data __initdata = {
607   - .slaves = hpb_dmae_slaves,
608   - .num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
609   - .channels = hpb_dmae_channels,
610   - .num_channels = ARRAY_SIZE(hpb_dmae_channels),
611   - .ts_shift = {
612   - [XMIT_SZ_8BIT] = 0,
613   - [XMIT_SZ_16BIT] = 1,
614   - [XMIT_SZ_32BIT] = 2,
615   - },
616   - .num_hw_channels = 44,
617   -};
618   -
619   -static struct resource hpb_dmae_resources[] __initdata = {
620   - /* Channel registers */
621   - DEFINE_RES_MEM(0xffc08000, 0x1000),
622   - /* Common registers */
623   - DEFINE_RES_MEM(0xffc09000, 0x170),
624   - /* Asynchronous reset registers */
625   - DEFINE_RES_MEM(0xffc00300, 4),
626   - /* Asynchronous mode registers */
627   - DEFINE_RES_MEM(0xffc00400, 4),
628   - /* IRQ for DMA channels */
629   - DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
630   -};
631   -
632   -static void __init r8a7779_register_hpb_dmae(void)
633   -{
634   - platform_device_register_resndata(NULL, "hpb-dma-engine",
635   - -1, hpb_dmae_resources,
636   - ARRAY_SIZE(hpb_dmae_resources),
637   - &dma_platform_data,
638   - sizeof(dma_platform_data));
639   -}
640   -
641   -static struct platform_device *r8a7779_early_devices[] __initdata = {
642   - &tmu0_device,
643   -};
644   -
645   -static struct platform_device *r8a7779_standard_devices[] __initdata = {
646   - &scif0_device,
647   - &scif1_device,
648   - &scif2_device,
649   - &scif3_device,
650   - &scif4_device,
651   - &scif5_device,
652   - &i2c0_device,
653   - &i2c1_device,
654   - &i2c2_device,
655   - &i2c3_device,
656   - &sata_device,
657   -};
658   -
659   -void __init r8a7779_add_standard_devices(void)
660   -{
661   -#ifdef CONFIG_CACHE_L2X0
662   - /* Shared attribute override enable, 64K*16way */
663   - l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
664   -#endif
665   - r8a7779_pm_init();
666   -
667   - r8a7779_init_pm_domains();
668   -
669   - platform_add_devices(r8a7779_early_devices,
670   - ARRAY_SIZE(r8a7779_early_devices));
671   - platform_add_devices(r8a7779_standard_devices,
672   - ARRAY_SIZE(r8a7779_standard_devices));
673   - r8a7779_register_hpb_dmae();
674   -}
675   -
676   -void __init r8a7779_add_early_devices(void)
677   -{
678   - early_platform_add_devices(r8a7779_early_devices,
679   - ARRAY_SIZE(r8a7779_early_devices));
680   -
681   - /* Early serial console setup is not included here due to
682   - * memory map collisions. The SCIF serial ports in r8a7779
683   - * are difficult to identity map 1:1 due to collision with the
684   - * virtual memory range used by the coherent DMA code on ARM.
685   - *
686   - * Anyone wanting to debug early can remove UPF_IOREMAP from
687   - * the sh-sci serial console platform data, adjust mapbase
688   - * to a static M:N virt:phys mapping that needs to be added to
689   - * the mappings passed with iotable_init() above.
690   - *
691   - * Then add a call to shmobile_setup_console() from this function.
692   - *
693   - * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
694   - * command line in case of the marzen board.
695   - */
696   -}
697   -
698   -static struct platform_device *r8a7779_late_devices[] __initdata = {
699   - &ehci0_device,
700   - &ehci1_device,
701   - &ohci0_device,
702   - &ohci1_device,
703   -};
704   -
705   -void __init r8a7779_init_late(void)
706   -{
707   - /* get USB PHY */
708   - phy = usb_get_phy(USB_PHY_TYPE_USB2);
709   -
710   - shmobile_init_late();
711   - platform_add_devices(r8a7779_late_devices,
712   - ARRAY_SIZE(r8a7779_late_devices));
713   -}
714   -
715   -#ifdef CONFIG_USE_OF
716   -void __init r8a7779_init_irq_dt(void)
717   -{
718   -#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
719   - void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000);
720   - void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000);
721   -#endif
722 65 gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
723 66  
724   -#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
725   - gic_init(0, 29, gic_dist_base, gic_cpu_base);
726   -#else
727 67 irqchip_init();
728   -#endif
  68 +
729 69 /* route all interrupts to ARM */
730 70 __raw_writel(0xffffffff, INT2NTSR0);
731 71 __raw_writel(0x3fffffff, INT2NTSR1);
... ... @@ -740,7 +80,7 @@
740 80  
741 81 #define MODEMR 0xffcc0020
742 82  
743   -u32 __init r8a7779_read_mode_pins(void)
  83 +static u32 __init r8a7779_read_mode_pins(void)
744 84 {
745 85 static u32 mode;
746 86 static bool mode_valid;
747 87  
748 88  
749 89  
... ... @@ -756,17 +96,24 @@
756 96 return mode;
757 97 }
758 98  
  99 +static void __init r8a7779_init_time(void)
  100 +{
  101 + r8a7779_clocks_init(r8a7779_read_mode_pins());
  102 + clocksource_of_init();
  103 +}
  104 +
759 105 static const char *const r8a7779_compat_dt[] __initconst = {
760 106 "renesas,r8a7779",
761 107 NULL,
762 108 };
763 109  
764 110 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
  111 + .smp = smp_ops(r8a7779_smp_ops),
765 112 .map_io = r8a7779_map_io,
766 113 .init_early = shmobile_init_delay,
  114 + .init_time = r8a7779_init_time,
767 115 .init_irq = r8a7779_init_irq_dt,
768 116 .init_late = shmobile_init_late,
769 117 .dt_compat = r8a7779_compat_dt,
770 118 MACHINE_END
771   -#endif /* CONFIG_USE_OF */
arch/arm/mach-shmobile/smp-r8a7779.c
Diff comments   View file @ ff20775
... ... @@ -23,7 +23,6 @@
23 23 #include <asm/cacheflush.h>
24 24 #include <asm/smp_plat.h>
25 25 #include <asm/smp_scu.h>
26   -#include <asm/smp_twd.h>
27 26  
28 27 #include "common.h"
29 28 #include "pm-rcar.h"
... ... @@ -55,14 +54,6 @@
55 54 [2] = &r8a7779_ch_cpu2,
56 55 [3] = &r8a7779_ch_cpu3,
57 56 };
58   -
59   -#if defined(CONFIG_HAVE_ARM_TWD) && !defined(CONFIG_ARCH_MULTIPLATFORM)
60   -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29);
61   -void __init r8a7779_register_twd(void)
62   -{
63   - twd_local_timer_register(&twd_local_timer);
64   -}
65   -#endif
66 57  
67 58 static int r8a7779_platform_cpu_kill(unsigned int cpu)
68 59 {