03 Nov, 2018
1 commit
-
Update SCFW API to the following commit:
"
("430d1e3646fbe75e339e18abf2330565eac906e0")
Author: Chuck Cannon
Date: Fri Nov 2 15:25:45 2018 -0500SCF-105: RN updates.
"Signed-off-by: Ranjani Vaidyanathan
29 Oct, 2018
35 commits
-
update the noc QoS setting for CPU & VPU on i.MX8MQ.
Signed-off-by: Bai Ping
Reviewed-by: Jian Li
(cherry picked from commit 45d2dcaecce6d83e5c4a7e9488c651a05b0f05ac) -
This patch adds SC_C_SYNC_CTRL into enum sc_ctrl_e to sync with SCU
firmware commit (SCF-151: Added new SC_C_SYNC_CTRL to
control both control signals at the same time.).Signed-off-by: Liu Ying
(cherry picked from commit 9e4a5892dad642f76e3bb0d46c77c4a59bbcae3d) -
Add PAD wakeup support for i.MX8 platforms with system
controller present, with PAD wakeup feature enabled,
the corresponding resource's power is no need to be
kept enabled when linux suspend, thus save a sub-system's
power consumption.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
(cherry picked from commit 3b5d781273b22461de9aaea337f9da9b2fdb643e) -
Signed-off-by: Daniel Baluta
Reviewed-by: Shengjiu Wang
(cherry picked from commit 8bc09ad559237c136f88d93bd696fe10dc4658db) -
Remove unused ROMCP clks and related as LPCG
no longer existsSigned-off-by: Teo Hall
Reviewed-by: Anson Huang
(cherry picked from commit 1c15332dffe7e41f0b9d367b96dd426798ec8b06) -
Add LCDIF PLL resource and clocks, and power domain for it.
Add Pixel link clocks and set it from bypass path.
Muxes were added so that the slices can choose the bypass input
(lcd_pxl_bypass_div and elcdif_pll_div).clk summary example:
lcd_pxl_bypass_div 2 2 24000000
lcd_pxl_sel 1 1 24000000
lcd_pxl_div 1 1 24000000
lcd_pxl_clk 1 1 24000000
elcdif_pll_div 1 1 792000000
elcdif_pll 2 2 792000000
lcd_sel 1 1 792000000
lcd_div 1 1 79200000
lcd_clk 1 1 79200000Signed-off-by: Adriana Reus
-
In order to replace the M4_MU# by the LSIO MU in the
RPMSG usage.
Define the PD and LPCG address of the LSIO MU for iMX8.Signed-off-by: Richard Zhu
-
To support lowest power mode for suspend, if no wakeup source
from non-secure partition is enabled, IRQSTEER can be powered
off when suspend, otherwise, IRQSTEER needs to be powered on
to support wakeup, so need to pass WU domain wakeup source
info to ATF, then ATF will decide if to power off IRQSTEER
when system suspend.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
Let Dom0 use hvc to trap to xen to communicate with SCU.
xen could reuse the MU used by Dom0 before. By reusing
the MU in Dom0, xen has power to control resources owned
by DomU.Signed-off-by: Peng Fan
-
- Sync with scu firmware commit 576011819ce3 (SCF-81: Added API to
control MIPI CSI calibration.) and commit 095a0d7dbc0b (SCF-85: Add
direct control of ENET IPG stop control)
- Add ipg stop misc controls for CONN ENET.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.So use the name of dsp instead of hifi to fix this
problem.Signed-off-by: Weiguang Kong
-
Add SC_C_SEL0 for imx8qm/qxp B0.
Signed-off-by: yuchou gan
-
Register clocks for CI_PI subsystem.
Reviewed-by: Sandor.Yu
Signed-off-by: Guoniu.Zhou
(cherry picked from commit d29308ec4fa29addd049c114520d7628e9e921d7) -
"
commit cfdb9821531da523fd1f01536eb67c8b8451477f
Author: Oliver Brown
Date: Tue Jan 2 07:46:06 2018 -0600dc: Add controls for display controller resets.
"Signed-off-by: Oliver Brown
-
Config NOC to limit bandwidth to 4GB for both VPU
and CPU to avoid lcdif flickering only when lcdif is enabled.Signed-off-by: Anson Huang
Acked-by: Peng Fan
Reviewed-by: Bai Ping
(cherry picked from commit 8ab89ebeb94a423792bf588bdf2354c5960d8f13) -
Add pre_timeout set and notification for i.mx8qm/qxp.
BuildInfo:
- SCFW 36ff24f3, IMX-MKIMAGE 05d3d4a7, ATF 93dd1cc
- U-Boot 2017.03-00684-g28c5243Signed-off-by: Robin Gong
Reviewed-by: Anson Huang -
On i.MX8MQ, the new revision SoC does NOT update the
revision info in ANATOP_DIGPROG register, to support
dynamic SOC id/revision detection, only reading info
from ANATOP_DIGPROG is not working now, change to read
SOC id/revision from ATF which is in secure world.The ATF will read the ANATOP_DIGPROG as well as ROM
version to decide the SOC revision.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
Support M4/A53 work together
1. add imx_src_is_m4_enabled
2. introduce a new dts dedicated for m4
3. add more pwm nodes
4. Since clk initialization is at very early stage, add m4 enabled check
in the beginning of clk code.Signed-off-by: Peng Fan
Reviewed-by: Richard Zhu -
Add busfreq driver support on i.MX8MQ. The busfreq driver is
mainly used for dynamic DDR frequency change for power saving
feature. When there is no peripheral or DMA device has direct
access to DDR memory, we can lower the DDR frequency to save
power. Currently, we support frequency setpoint for LPDDR4:(1): 3200mts, the DDRC core clock is sourced from 800MHz
dram_pll, the DDRC apb clock is 200MHz.(2): 400mts, the DDRC core clock is source from sys1_pll_400m,
the DDRC apb clock is is sourced from sys1_pll_40m.(3): 100mts, the DDRC core clock is sourced from sys1_pll_100m,
the DDRC apb clock is sourced from sys1_pll_40m.In our busfreq driver, we have three mode supported:
* high bus mode 3200mts;
* audio bus mode 400mts;
* low bus mode 100mts;The actual DDR frequency is done in ARM trusted firmware by calling
the SMCC SiP service call.BuildInfo:
- IMX-MKIMAGE: 05d3d4a7d7, ATF: 724cc2b890
- SPL/Uboot: f72c10d2db;Signed-off-by: Bai Ping
Reviewed-by: Anson Huang -
This watchdog driver is a virtual driver in Linux and call ATF interface
where call SCFW eventually. In SCFW, it's done by SCU timer tick instead
of hardware watchdog.This is why we have to call ATF because such system
resource owned by secure patition.Currently, booard reset happen if not
ping this software watchdog in time in linux side, may change to partition
reboot once SCFW support this feature in the future.
BuildInfo:
- SCFW 93c142a9, IMX-MKIMAGE 2522fd70, ATF f2547fb
- U-Boot 2017.03-00097-gd7599cfSigned-off-by: Robin Gong
Reviewed-by: Anson Huang -
There're two M4 I2C instances in MX8QM.
Signed-off-by: Dong Aisheng
-
For system controller RTC, as it belongs SC_R_SYSTEM,
and SC_R_SYSTEM is assigned in ARM-Trusted-Firmware,
so here needs to use SIP to trap into ATF to do set
time, or system controller firmware will return
error since linux kernel does NOT own this system
resource.Signed-off-by: Anson Huang
-
Add SIP cpu-freq support, the CPU hardware frequency
scale will be performed by ARM Trusted Firmware,
and add cpu-freq suspend support, MAX frequency will
be used during suspend.Signed-off-by: Anson Huang
-
mipi csi0/1 clock gate register address swapped.
It will cause mipi csi0/1 failed to work.Signed-off-by: Sandor Yu
-
Add cm40 I2C clock for imx8qxp
Signed-off-by: Shengjiu Wang
-
Add power domain names for i.MX8MQ, currently only
11 power domains support runtime ON/OFF.Signed-off-by: Anson Huang
-
add clk for dsi0 i2c0
Signed-off-by: Gao Pan
-
This patch is to refine the imx8 soc revision support. The imx8qm and
imx8qxp will go through the SCU API to get the silicon ID and REVISION.
imx8mq will go through the anatop interface to get the ID/REV.Since the silicon ID/REV need be set as early as possible, thus refine it
by using the early_initcall for the early initialization. For the SCU API
interface, this need be called after the MU interface initialized.Signed-off-by: Jason Liu
Reviewed-by: Anson Huang -
Add generic power domain driver support on i.mx8mq. The power
domain on/off operations need to use the SIP service call to
trap into secure monitor to handle it.Signed-off-by: Bai Ping
-
Add i.MX8MQ clock driver support.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping -
Add i.MX8MQ PSCI GPC virtual driver support.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping -
This patch adds some clocks support for DC and MIPI-LVDS subsystems.
Signed-off-by: Liu Ying
-
Cleanup audio LPCGs: add missing, fix names, remove unneeded.
Signed-off-by: Viorel Suman
-
Add i.MX8 SCFW API support.
Based on below commit:
(fcd0efb5f2550712bd7d27f1279e51f7f687f71d)
Fix MX8 MU driver to follow Linux coding conventions.
Remove unused functions.Signed-off-by: Anson Huang
Signed-off-by: Ranjani VaidyanathanAdded to drivers/soc/imx instead of drivers/soc/imx8
Skipped imx8 imx_rpmsg codeSigned-off-by: Leonard Crestez
-
As A9 and M4 share many resources on i.MX6SX, especially for
clk and power related resource, so we need to handle the hardware
conflict between these two cores, there are two cases that we
need to consider currently:clk management: for every clk node, only when both A9 and
M4 do NOT need it, then we can disable it from hardware;Here we use MU and hardware SEMA4 to achieve our goal, MU is
for communiation between A9 and M4, SEMA4 is to protect the
shared memory.For clk management, we use shared memory to maintain the clk
status for both A9 and M4 side, and this shared memory is
protected by hardware SEMA4, A9 and M4 will maintain their
own clk tree info in their SW environment, and get other
CORE's clk tree info from shared memory to decide whether
to perform a hardware setting change when they plan to.Signed-off-by: Anson Huang
Also made SOC_IMX6SX select IMX_SEMA4 as part of this commit to fix
build failures.Signed-off-by: Leonard Crestez
03 Aug, 2018
1 commit
-
[ Upstream commit 1c74d5c0de0c2cc29fef97a19251da2ad6f579bd ]
Currently we are enabling handling of interrupts specific to Tegra124+
which happen to overlap with previous generations. Let's specify
interrupts mask per SoC generation for consistency and in a preparation
of squashing of Tegra20 driver into the common one that will enable
handling of GART faults which may be undesirable by newer generations.Signed-off-by: Dmitry Osipenko
Signed-off-by: Thierry Reding
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
21 Jun, 2018
1 commit
-
[ Upstream commit 144345a4a8c3b497a3f60d3af9d6071a37660186 ]
If CONFIG_RASPBERRYPI_FIRMWARE=n:
drivers/gpio/gpio-raspberrypi-exp.c: In function ‘rpi_exp_gpio_get_polarity’:
drivers/gpio/gpio-raspberrypi-exp.c:71: warning: ‘get.polarity’ is used uninitialized in this function
drivers/gpio/gpio-raspberrypi-exp.c: In function ‘rpi_exp_gpio_get_direction’:
drivers/gpio/gpio-raspberrypi-exp.c:150: warning: ‘get.direction’ is used uninitialized in this functionThe dummy firmware interface functions return 0, which means success,
causing subsequent code to make use of the never initialized output
parameter.Fix this by making the dummy functions return an error code (-ENOSYS)
instead.Note that this assumes the firmware always fills in the requested data
in the CONFIG_RASPBERRYPI_FIRMWARE=y case.Fixes: d45f1a563b92dac7 ("staging: vc04_services: fix up rpi firmware functions")
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Eric Anholt
Signed-off-by: Florian Fainelli
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
30 May, 2018
2 commits
-
[ Upstream commit f3205de98db2fc8083796dd5ad81b191e436fab8 ]
As of today we use hardcoded MCIP debug mask, so if we launch
kernel via debugger and kick fever cores than HW has all cpus
hang at the momemt of setup MCIP debug mask.So update MCIP debug mask when the new cpu came online, instead of
use hardcoded MCIP debug mask.Signed-off-by: Eugeniy Paltsev
Signed-off-by: Vineet Gupta
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman -
[ Upstream commit 07423d00a2b2a71a97e4287d9262cb83c4c4c89f ]
In SMP systems, GFRC is used for clocksource. However by default the
counter keeps running even when core is halted (say when debugging via a
JTAG debugger). This confuses Linux timekeeping and triggers flase RCU stall
splat such as below:| [ARCLinux]# while true; do ./shm_open_23-1.run-test ; done
| Running with 1000 processes for 1000 objects
| hrtimer: interrupt took 485060 ns
|
| create_cnt: 1000
| Running with 1000 processes for 1000 objects
| [ARCLinux]# INFO: rcu_preempt self-detected stall on CPU
| 2-...: (1 GPs behind) idle=a01/1/0 softirq=135770/135773 fqs=0
| INFO: rcu_preempt detected stalls on CPUs/tasks:
| 0-...: (1 GPs behind) idle=71e/0/0 softirq=135264/135264 fqs=0
| 2-...: (1 GPs behind) idle=a01/1/0 softirq=135770/135773 fqs=0
| 3-...: (1 GPs behind) idle=4e0/0/0 softirq=134304/134304 fqs=0
| (detected by 1, t=13648 jiffies, g=31493, c=31492, q=1)Starting from ARC HS v3.0 it's possible to tie GFRC to state of up-to 4
ARC cores with help of GFRC's CORE register where we set a mask for
cores which state we need to rely on.We update cpu mask every time new cpu came online instead of using
hardcoded one or using mask generated from "possible_cpus" as we
want it set correctly even if we run kernel on HW which has fewer cores
than expected (or we launch kernel via debugger and kick fever cores
than HW has)Note that GFRC halts when all cores have halted and thus relies on
programming of Inter-Core-dEbug register to halt all cores when one
halts.Signed-off-by: Alexey Brodkin
Signed-off-by: Eugeniy Paltsev
Signed-off-by: Vineet Gupta
[vgupta: rewrote changelog]
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
