14 Feb, 2008
2 commits
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The TLB entry for the user address doesn't exist at the time we
want to flush the caches, so use the page address. Note that processor
configurations with cache-aliasing issues are treated separately.Signed-off-by: Chris Zankel
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Signed-off-by: Lucas Woods
Signed-off-by: Andrew Morton
Signed-off-by: Christian Zankel
28 Aug, 2007
1 commit
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Add support for processors that have cache-aliasing issues, such as
the Stretch S5000 processor. Cache-aliasing means that the size of
the cache (for one way) is larger than the page size, thus, a page
can end up in several places in cache depending on the virtual to
physical translation. The method used here is to map a user page
temporarily through the auto-refill way 0 and of of the DTLB.
We probably will want to revisit this issue and use a better
approach with kmap/kunmap.Signed-off-by: Chris Zankel