18 Jul, 2019
1 commit
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Pull dmaengine updates from Vinod Koul:
- Add support in dmaengine core to do device node checks for DT devices
and update bunch of drivers to use that and remove open coding from
drivers- New driver/driver support for new hardware, namely:
- MediaTek UART APDMA
- Freescale i.mx7ulp edma2
- Synopsys eDMA IP core version 0
- Allwinner H6 DMA- Updates to axi-dma and support for interleaved cyclic transfers
- Greg's debugfs return value check removals on drivers
- Updates to stm32-dma, hsu, dw, pl330, tegra drivers
* tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (68 commits)
dmaengine: Revert "dmaengine: fsl-edma: add i.mx7ulp edma2 version support"
dmaengine: at_xdmac: check for non-empty xfers_list before invoking callback
Documentation: dmaengine: clean up description of dmatest usage
dmaengine: tegra210-adma: remove PM_CLK dependency
dmaengine: fsl-edma: add i.mx7ulp edma2 version support
dt-bindings: dma: fsl-edma: add new i.mx7ulp-edma
dmaengine: fsl-edma-common: version check for v2 instead
dmaengine: fsl-edma-common: move dmamux register to another single function
dmaengine: fsl-edma: add drvdata for fsl-edma
dmaengine: Revert "dmaengine: fsl-edma: support little endian for edma driver"
dmaengine: rcar-dmac: Reject zero-length slave DMA requests
dmaengine: dw: Enable iDMA 32-bit on Intel Elkhart Lake
dmaengine: dw-edma: fix semicolon.cocci warnings
dmaengine: sh: usb-dmac: Use [] to denote a flexible array member
dmaengine: dmatest: timeout value of -1 should specify infinite wait
dmaengine: dw: Distinguish ->remove() between DW and iDMA 32-bit
dmaengine: fsl-edma: support little endian for edma driver
dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width"
dmagengine: pl330: add code to get reset property
dt-bindings: pl330: document the optional resets property
...
25 Jun, 2019
1 commit
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The commit
080edf75d337 ("dmaengine: hsu: set HSU_CH_MTSR to memory width")
has been mistakenly submitted. The further investigations show that
the original code does better job since the memory side transfer size
has never been configured by DMA users.As per latest revision of documentation: "Channel minimum transfer size
(CHnMTSR)... For IOSF UART, maximum value that can be programmed is 64 and
minimum value that can be programmed is 1."This reverts commit 080edf75d337d35faa6fc3df99342b10d2848d16.
Fixes: 080edf75d337 ("dmaengine: hsu: set HSU_CH_MTSR to memory width")
Signed-off-by: Andy Shevchenko
Signed-off-by: Vinod Koul
19 Jun, 2019
1 commit
-
Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundationthis program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: Thomas Gleixner
Reviewed-by: Enrico Weigelt
Reviewed-by: Kate Stewart
Reviewed-by: Allison Randal
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman
21 May, 2019
1 commit
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Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:GPL-2.0-only
Signed-off-by: Thomas Gleixner
Signed-off-by: Greg Kroah-Hartman
07 Oct, 2018
1 commit
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dma_slave_config direction was marked as deprecated quite some
time back, remove the usage from this driver so that the field
can be removedAcked-by: Andy Shevchenko
Signed-off-by: Vinod Koul
10 Jul, 2018
1 commit
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It appears that the driver misses the support of dmaengine_terminate_sync().
Since many of callers expects this behaviour implement the new
device_synchronize() callback to allow proper synchronization when stopping
a channel.Fixes: b36f09c3c441 ("dmaengine: Add transfer termination synchronization support")
Signed-off-by: Andy Shevchenko
Signed-off-by: Vinod Koul
19 Jan, 2017
1 commit
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Starting from Tangier B0 and continuing on Anniedale the HSU DMA interrupt
line is actually shared with UART. Handling them independently is racy and
quite often comes with the following traceback.irq 54: nobody cared (try booting with the "irqpoll" option)
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.9.0-rc6-edison64-86244934+ #1
Hardware name: Intel Corporation Merrifield/BODEGA BAY, BIOS 542 2015.01.21:18.19.48
ffff88003f203eb0 ffffffff8130e718 ffff880032627000 ffff88003262709c
ffff88003f203ed8 ffffffff810a3960 ffff880032627000 0000000000000000
ffff880032627000 ffff88003f203f10 ffffffff810a3cc7 ffff880032627000
Call Trace:
[] dump_stack+0x4d/0x65
[] __report_bad_irq+0x30/0xc0
[] note_interrupt+0x227/0x270
[] handle_irq_event_percpu+0x40/0x50
[] handle_irq_event+0x27/0x50
[] handle_fasteoi_irq+0x85/0x150
[] handle_irq+0x6e/0x120
[] ? _local_bh_enable+0x1c/0x50
[] do_IRQ+0x46/0xd0
[] common_interrupt+0x7f/0x7f
[] ? mwait_idle+0x7d/0x140
[] arch_cpu_idle+0xa/0x10
[] default_idle_call+0x20/0x30
[] cpu_startup_entry+0x16d/0x1d0
[] rest_init+0x6d/0x70
[] start_kernel+0x3e2/0x3ef
[] x86_64_start_reservations+0x38/0x3a
[] x86_64_start_kernel+0xea/0xed
handlers:
[] serial8250_interrupt
Disabling IRQ #54Fix this by handling interrupt only in one place.
The issue is discussed here: https://github.com/andy-shev/linux/issues/5
Moreover this also fixes another bug when Rx DMA returns wrong residue and we
can't rely on it.Reviewed-by: Heikki Krogerus
Signed-off-by: Andy Shevchenko
Acked-by: Vinod Koul
Signed-off-by: Greg Kroah-Hartman
25 Nov, 2016
1 commit
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There is new API in place which provides allocation mechanism of interrupts for
PCI devices. Use it in the HSU DMA driver.Signed-off-by: Andy Shevchenko
Signed-off-by: Vinod Koul
02 Sep, 2016
1 commit
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Since we have nice macro IRQ_RETVAL() we would use it to convert a flag of
handled interrupt from int to irqreturn_t.The rationale of doing this is:
a) hence we implicitly mark hsu_dma_do_irq() as an auxiliary function that
can't be used as interrupt handler directly, and
b) to be in align with serial driver which is using serial8250_handle_irq()
that returns plain int by design.Signed-off-by: Andy Shevchenko
Signed-off-by: Greg Kroah-Hartman
26 Jun, 2016
1 commit
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To allow other code to safely read DMA Channel Status Register (where
the register attribute for Channel Error, Descriptor Time Out &
Descriptor Done fields are read-clear), export hsu_dma_get_status().
hsu_dma_irq() is renamed to hsu_dma_do_irq() and requires Status
Register value to be passed in.Signed-off-by: Chuah, Kim Tatt
Acked-by: Andy Shevchenko
Reviewed-by: Heikki Krogerus
Signed-off-by: Greg Kroah-Hartman
20 May, 2016
1 commit
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Pull dmaengine updates from Vinod Koul:
"This time round the update brings in following changes:- new tegra driver for ADMA device
- support for Xilinx AXI Direct Memory Access Engine and Xilinx AXI
Central Direct Memory Access Engine and few updates to this driver- new cyclic capability to sun6i and few updates
- slave-sg support in bcm2835
- updates to many drivers like designware, hsu, mv_xor, pxa, edma,
qcom_hidma & bam"* tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (84 commits)
dmaengine: ioatdma: disable relaxed ordering for ioatdma
dmaengine: of_dma: approximate an average distribution
dmaengine: core: Use IS_ENABLED() instead of checking for built-in or module
dmaengine: edma: Re-evaluate errors when ccerr is triggered w/o error event
dmaengine: qcom_hidma: add support for object hierarchy
dmaengine: qcom_hidma: add debugfs hooks
dmaengine: qcom_hidma: implement lower level hardware interface
dmaengine: vdma: Add clock support
Documentation: DT: vdma: Add clock support for dmas
dmaengine: vdma: Add config structure to differentiate dmas
MAINTAINERS: Update Tegra DMA maintainers
dmaengine: tegra-adma: Add support for Tegra210 ADMA
Documentation: DT: Add binding documentation for NVIDIA ADMA
dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access Engine
Documentation: DT: vdma: update binding doc for AXI CDMA
dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine
Documentation: DT: vdma: update binding doc for AXI DMA
dmaengine: vdma: Rename xilinx_vdma_ prefix to xilinx_dma
dmaengine: slave means at least one of DMA_SLAVE, DMA_CYCLIC
dmaengine: mv_xor: Allow selecting mv_xor for mvebu only compatible SoC
...
05 Apr, 2016
6 commits
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This tells, for example, IOMMU what the maximum size of a segment
the DMA controller can send.Signed-off-by: Andy Shevchenko
Signed-off-by: Vinod Koul -
The timeout capability is only available on the so called DMA write channels,
i.e. associated with UART Rx FIFO. It means we don't need to check the
direction of the channel to handle timeouts.Signed-off-by: Andy Shevchenko
Signed-off-by: Vinod Koul -
Current code allows only up to 3 descriptors to be programmed to the hardware
since it is used wrong calculations. Change % to min_t() to allow as many
descriptors as user supplied. At once it could be programmed up to 4
descriptors due to hardware limitations.The issue was found under stress test, so it might not bother ordinary users.
Signed-off-by: Andy Shevchenko
Signed-off-by: Vinod Koul -
There is a typo in documentation regarding to descriptor empty bit (DESCE)
which is set to 1 when descriptor is empty. Thus, status register at the end of
a transfer usually returns all DESCE bits set and thus it will never be zero.Moreover, there are 2 bits (CDESC) that encode current descriptor, on which
interrupt has been asserted. In case when we have few descriptors programmed we
might have non-zero value.Remove DESCE and CDESC bits from DMA channel status register (HSU_CH_SR) when
reading it.Fixes: 2b49e0c56741 ("dmaengine: append hsu DMA driver")
Cc: stable@vger.kernel.org
Signed-off-by: Andy Shevchenko
Signed-off-by: Vinod Koul -
The commit f0579c8ceaf1 ("dmaengine: hsu: speed up residue calculation")
speeded up calculation of the queued descriptor but broke the initial residue
value for active descriptor.In accordance with documentation the hardware descriptor is updated each time
DMA transfered some bytes. It means we have to calculate a sum of lengths of
non-submitted hardware descriptors and whatever current values in the hardware.
Do this straightforward.Fixes: f0579c8ceaf1 ("dmaengine: hsu: speed up residue calculation")
Cc: stable@vger.kernel.org
Signed-off-by: Andy Shevchenko
Signed-off-by: Vinod Koul -
HSU_CH_MTSR register should be programmed to a minimum size to transfer. This
size on a memory side of the transfer. Program it accordingly.Signed-off-by: Andy Shevchenko
Signed-off-by: Vinod Koul
05 Dec, 2015
1 commit
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There is no need to calculate an overall length of the descriptor each time we
call for DMA transfer status. Instead we do this at descriptor allocation stage
and keep the stored length for further usage.Signed-off-by: Andy Shevchenko
Signed-off-by: Vinod Koul
18 Oct, 2015
2 commits
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There are no platforms where it's not possible to calculate
the number of channels based on IO space length, and since
that is the only purpose for struct hsu_dma_platform_data,
removing it.Suggested-by: Andy Shevchenko
Signed-off-by: Heikki Krogerus
Acked-by: Vinod Koul
Acked-by: Andy Shevchenko
Signed-off-by: Greg Kroah-Hartman -
HSU (High Speed UART) DMA engine, like the name suggests, is
an integrated DMA engine for UART and UART alone. Therefore,
making the UART drivers responsible of selecting it and
removing the user selectable option for it. The UARTs with
this DMA engine can always select HSU_DMA when
SERIAL_8250_DMA option is enabled.Suggested-by: Andy Shevchenko
Signed-off-by: Heikki Krogerus
Acked-by: Vinod Koul
Acked-by: Andy Shevchenko
Signed-off-by: Greg Kroah-Hartman
16 Jul, 2015
1 commit
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All hardware accesses are done under virtual channel lock. That's why specific
channel lock is excessive and can be removed safely. This has been tested on
Intel Medfield and Merrifield.Signed-off-by: Andy Shevchenko
Signed-off-by: Vinod Koul
02 Jun, 2015
1 commit
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The vd->node is removed from the lists when the transfer started so the
vchan_get_all_descriptors() will not find it. This results memory leak.Signed-off-by: Peter Ujfalusi
[andy: fix the typo to prevent a compilation error]
Signed-off-by: Andy Shevchenko
Signed-off-by: Vinod Koul
23 Apr, 2015
1 commit
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HSU_DMA is selected by the HSU_DMA_PCI driver, this should be user selected
so remove the user prompt for thisSigned-off-by: Vinod Koul
Signed-off-by: Linus Torvalds
27 Mar, 2015
3 commits
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The GFP_ATOMIC is too strict, and DMAEngine documentation make an advice to use
GFP_NOWAIT. This patch does the conversion.Signed-off-by: Andy Shevchenko
Acked-by: Vinod Koul
Signed-off-by: Greg Kroah-Hartman -
There are few places where the implemented pieces of code are not needed, i.e.:
- direction can't be wrong in hsu_dma_chan_start()
- desc->active set to 0 by kzalloc
- DMAEngine is NULL-aware when call ->device_alloc_chan_resources()Signed-off-by: Andy Shevchenko
Acked-by: Vinod Koul
Signed-off-by: Greg Kroah-Hartman -
Intel Tangier is known to have the HSU DMA IP as PCI device 00:05.0. The patch
adds the ID as found on Intel Edison board to the PCI device table.Signed-off-by: Andy Shevchenko
Signed-off-by: Greg Kroah-Hartman
07 Mar, 2015
1 commit
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The HSU DMA is developed to support High Speed UART controllers found in
particular on Intel MID platforms such as Intel Medfield.The existing implementation is tighten to the drivers/tty/serial/mfd.c driver
and has a lot of disadvantages. Besides that we would like to get rid of the
old HS UART driver in regarding to extending the 8250 which supports generic
DMAEngine API. That's why the current driver has been developed.Signed-off-by: Andy Shevchenko
Signed-off-by: Greg Kroah-Hartman