17 Jan, 2020
1 commit
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In case of error, the function devm_ioremap() returns NULL pointer not
ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Signed-off-by: Wei Yongjun
Signed-off-by: Kishon Vijay Abraham I
14 Jan, 2020
13 commits
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The Allwinner A80 SoCs have a USB PHY controller that is used by Linux,
with a matching Device Tree binding.Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.Reviewed-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I -
commit 95f1061f715e ("phy: intel-lgm-emmc: Add support for eMMC PHY")
introduces the below warningWARNING: modpost: missing MODULE_LICENSE() in
drivers/phy/intel/phy-intel-emmc.oFix it by adding missing MODULE_LICENSE.
Signed-off-by: Ramuthevar Vadivel Murugan
Reported-by: Stephen Rothwell
Signed-off-by: Kishon Vijay Abraham I -
Based on this GPIO state we need to configure LN10
bit to swap lane0 and lane1 if required (flipped connector).Type-C companions typically need some time after the cable is
plugged before and before they reflect the correct status of
Type-C plug orientation on the DIR line.Type-C Spec specifies CC attachment debounce time (tCCDebounce)
of 100 ms (min) to 200 ms (max).Use the DT property to figure out if we need to add delay
or not before sampling the Type-C DIR line.Signed-off-by: Roger Quadros
Signed-off-by: Sekhar Nori
Reviewed-by: Jyri Sarha
Signed-off-by: Kishon Vijay Abraham I -
This is an optional GPIO, if specified will be used to
swap lane 0 and lane 1 based on GPIO status. This is required
to achieve plug flip support for USB Type-C.Type-C companions typically need some time after the cable is
plugged before and before they reflect the correct status of
Type-C plug orientation on the DIR line.Type-C Spec specifies CC attachment debounce time (tCCDebounce)
of 100 ms (min) to 200 ms (max).Allow the DT node to specify the time (in ms) that we need
to wait before sampling the DIR line.Signed-off-by: Roger Quadros
Cc: Rob Herring
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I -
Some platforms e.g. J721e need lane swap register
to be programmed before reset is deasserted.
This patch ensures that we propagate the phy_reset
back to the reset controller driver.Signed-off-by: Roger Quadros
Signed-off-by: Sekhar Nori
Reviewed-by: Jyri Sarha
Signed-off-by: Kishon Vijay Abraham I -
The pointer regmap is being initialized with a value that is never
read and it is being updated later with a new value from
phy->regmap_common_cdb. The initialization is redundant and can be
removed.Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
Signed-off-by: Kishon Vijay Abraham I -
Allow DisplayPort PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The configuration structure is used for reconfiguration of
DisplayPort PHYs during link training operation.The parameters added here are the ones defined in the DisplayPort
spec v1.4 which include link rate, number of lanes, voltage swing
and pre-emphasis.Add the DisplayPort phy mode to the generic phy_mode enum.
Signed-off-by: Yuti Amonkar
Reviewed-by: Maxime Ripard
Reviewed-by: Jyri Sarha
Signed-off-by: Kishon Vijay Abraham I -
Some of the phy drivers can be compile tested to increase build
coverage.Signed-off-by: Krzysztof Kozlowski
Acked-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
Adjust indentation from spaces to tab (+optional two spaces) as in
coding style.Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Stanley Chu
Acked-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
Add support for eMMC PHY on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
Reviewed-by: Andy Shevchenko
Signed-off-by: Kishon Vijay Abraham I -
Add a YAML schema to use the host controller driver with the
eMMC PHY on Intel's Lightning Mountain SoC.Signed-off-by: Ramuthevar Vadivel Murugan
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I -
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig), two divider clocks and supports
resets for each of the lanes.[jsarha@ti.com: Add support for Torrent(10G) SERDES wrapper]
Signed-off-by: Jyri Sarha
Signed-off-by: Kishon Vijay Abraham I -
Add DT binding documentation for WIZ (SERDES wrapper). WIZ is *NOT* a
PHY but a wrapper used to configure some of the input signals to the
SERDES. It is used with both Sierra(16G) and Torrent(10G) serdes.Signed-off-by: Kishon Vijay Abraham I
[jsarha@ti.com: Add separate compatible for Sierra(16G) and Torrent(10G)
SERDES]
Signed-off-by: Jyri Sarha
Reviewed-by: Rob Herring
08 Jan, 2020
26 commits
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commit 44d30d622821d3b ("phy: cadence: Add driver for Sierra PHY"),
incorrectly used parent device pointer to get driver data. Fix it here.Signed-off-by: Kishon Vijay Abraham I
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Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz
as specified in "Common Module Clock Configurations" of the Cadence
Sierra 16FFC Multi-Protocol PHY PMA Specification. It is set to 25MHz
since the only user of Cadence Sierra SERDES, TI J721E SoC provides
input clock frequency of 100MHz. For other frequencies,
cmn_refclk_dig_div/cmn_refclk1_dig_div should be configured
based on the "Common Module Clock Configurations".Signed-off-by: Kishon Vijay Abraham I
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Sierra SERDES IP supports upto 16 lanes (though not all of it
will be enabled in a platform). Allow Sierra driver to support a
maximum of upto 16 lanes.Signed-off-by: Kishon Vijay Abraham I
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Check for PLL lock during PHY power on.
Signed-off-by: Kishon Vijay Abraham I
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A link may have multiple lanes each with a separate reset. Get
reset control "array" in order to reset all the lanes associated
with the link.Signed-off-by: Kishon Vijay Abraham I
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The existing configuration done in Cadence Sierra driver is only for
reference and is not used in any platforms. Remove them and configure
both lane cdb and common cdb registers to be used with external
SSC configuration. This is validated in TI J721E platform.Signed-off-by: Anil Varughese
Signed-off-by: Kishon Vijay Abraham I -
No functional change. Modify register offset macro names to be in sync with
Sierra user guide.Signed-off-by: Kishon Vijay Abraham I
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Instead of invoking cdns_sierra_phy_init() from probe, add it in
phy_ops so that it's initialized when the PHY consumer invokes
phy_init()Signed-off-by: Kishon Vijay Abraham I
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SERDES_16G in TI's J721E SoC uses Cadence Sierra PHY. Add
support to use Cadence Sierra driver in J721E SoC.Signed-off-by: Kishon Vijay Abraham I
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Use "regmap" for read and write to Sierra registers. This is in
perparation for adding SERDES_16G support present in TI's J721E
SoC.Signed-off-by: Kishon Vijay Abraham I
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Certain platforms like TI J721E using Cadence Sierra Serdes
doesn't provide explicit phy_clk and reset (APB reset) control.
Make them optional here.Signed-off-by: Kishon Vijay Abraham I
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Add DT binding documentation for Sierra PHY IP used in TI's J721E
SoC.Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring -
Add support for 7211 USB wake. Disable all possible 7211 USB logic
for S2/S5 if USB wake is not enabled.On the 7211, the XHCI wake signal was not connected properly and
only goes to the USB1_USB1_CTRL_TP_DIAG1 diagonstic register.
The workaround is to have VPU code running that polls for the
proper bit in the DIAG register and to wake the system when
the bit is asserted.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
This is a result of the USB 2.0 clocks not being disabled/enabled
during suspend/resume on XHCI only systems.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
The BDC "Read Transaction Size" needs to be changed from 1024
bytes to 256 bytes to prevent occasional transaction failures.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
When there is no device connected and FSM is enabled, the XHCI puts
the PHY into suspend mode. When the PHY is put into suspend mode
the USB LDO powers down the PHY. This causes the MDIO to be
inaccessible and its registers reset to default. The fix is to
disable FSM.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
Handle defer on clk_get because the new SCMI clock driver comes
up after this driver.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
The 7211b0 has added the STB XHCI Synopsys controller and it
will be used instead of the RPi based DWC USB controller. The new
Synopsys XHCI controller core is the same one that is used on the
7216, but because of the way the STB USB PHY is used on both the A0
and B0, some of the PHY control is different.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
The 7216 has the new USB XHCI controller from Synopsys. While
this new controller and the PHY are similar to the STB versions,
the major differences are:- Many of the registers and fields in the CTRL block have been
removed or changed.
- A new set of Synopsys control registers, BCHP_USB_XHCI_GBL, were
added.
- MDIO functionality has been replaced with direct access registers
in the BCHP_USB_XHCI_GBL block.
- Power up PHY defaults that had to be changed by MDIO in previous
chips will now power up with the correct defaults.A new init module was created for this new Synopsys USB controller.
A new compatible string was added and the driver will dispatch
into one of two init modules based on it. A "reg-names" field was
added so the driver can more easily get optional registers.
A DT bindings document was also added for this driver.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
Add support for bcm7216 and bcm7211
Signed-off-by: Al Cooper
Reviewed-by: Rob Herring
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
The driver is being restructured in preparation for adding support
for the new Synopsys USB conroller on the 7216. Since all the bugs
and work-arounds in previous STB chips are supposed to be fixed,
most of the code in phy-brcm-usb-init.c is not needed. Instead of
adding more complexity to the already complicated phy-brcm-usb-init.c
module, the driver will be restructured to use a vector table to
dispatch into different C modules for the different controllers.There was also some general cleanup done including some ipp setup
code that was incorrect.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
Add the ability to handle USB wake events from USB devices when
in S2 mode. Typically there is some additional configuration
needed to tell the USB device to generate the wake event when
suspended but this varies with the different USB device classes.
For example, on USB Ethernet dongles, ethtool should be used to
enable the magic packet wake functionality in the dongle.
NOTE: This requires that the "power/wakeup" sysfs entry for
the USB device generating the wakeup be set to "enabled".This functionality requires a special hardware sideband path that
will trigger the AON_PM_L2 interrupt needed to wake the system from
S2 even though the USB host controllers are in IDDQ (low power state)
and most USB related clocks are shut off. For the sideband signaling
to work we need to leave the usbx_freerun clock running, but this
clock consumes very little power by design. There's a bug in the
XHCI wake hardware so only EHCI/OHCI wake is currently supported.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
Currently the Phy driver will put the USB phys into the max
power saving mode (IDDQ) when there is no corresponding XHCI, EHCI
or OHCI client (through rmmod, unbind or if the driver is not
builtin). This change will also put the Phys into IDDQ mode
on suspend so that S2 will get the additional power savings.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
The BRCM USB Phy, ohci, ehci and xhci drivers all use the USB clocks
but not all drivers use the clk_prepare_enable/clk_disable_unprepare
versions to enable/disable the clocks. This change gets all drivers
using the prepare version.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
When the EHCI controller received a 512 byte USB packet that
had to be broken into 2 256 byte bursts across the SCB bus AND
there was a following 512 byte USB packet, the second burst of
data from the first packet was sometimes being lost. If the
burst size was changed to 128 bytes via the EBR_SCB_SIZE field
in the USB_CTRL_EBRIDGE register we'd see the 4th 128 byte burst
of the first packet being lost. This problem became much worse
if other threads were running that accessed memory, like a memcpy
test. Setting the EBR_SCB_SIZE to 512, which prevents breaking
the EHCI USB packet (max size of 512 bytes) into bursts, fixed
the problem.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and
then deassert it, so add the QPHY_SW_RESET register which does this.Signed-off-by: Vinod Koul
Reviewed-by: Manu Gautam
Reviewed-by: Can Guo
Signed-off-by: Kishon Vijay Abraham I
