30 Dec, 2020
1 commit
-
commit 5626308bb94d9f930aa5f7c77327df4c6daa7759 upstream.
pxa2xx_spi_remove() accesses the driver's private data after calling
spi_unregister_controller() even though that function releases the last
reference on the spi_controller and thereby frees the private data.Fix by switching over to the new devm_spi_alloc_master/slave() helper
which keeps the private data accessible until the driver has unbound.Fixes: 32e5b57232c0 ("spi: pxa2xx: Fix controller unregister order")
Signed-off-by: Lukas Wunner
Cc: # v2.6.17+: 5e844cc37a5c: spi: Introduce device-managed SPI controller allocation
Cc: # v2.6.17+: 32e5b57232c0: spi: pxa2xx: Fix controller unregister order
Cc: # v2.6.17+
Link: https://lore.kernel.org/r/5764b04d4a6e43069ebb7808f64c2f774ac6f193.1607286887.git.lukas@wunner.de
Signed-off-by: Mark Brown
Signed-off-by: Greg Kroah-Hartman
17 Jul, 2020
1 commit
-
Since ACPI_PTR() is used to NULLify the value when !CONFIG_ACPI,
struct 'pxa2xx_spi_acpi_match' becomes defined but unused.Fixes the following W=1 kernel build warning(s):
drivers/spi/spi-pxa2xx.c:1435:36: warning: ‘pxa2xx_spi_acpi_match’ defined but not used [-Wunused-const-variable=]
1435 | static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
| ^~~~~~~~~~~~~~~~~~~~~Signed-off-by: Lee Jones
Cc: Daniel Mack
Cc: Haojian Zhuang
Cc: Robert Jarzmik
Link: https://lore.kernel.org/r/20200717135424.2442271-14-lee.jones@linaro.org
Signed-off-by: Mark Brown
07 Jul, 2020
1 commit
-
…dde <mkl@pengutronix.de>:
Hello,
this series first fixes the calculation of the clock rate. The driver will
round up to the nearest clock rate instead of rounding down. Resulting in SPI
devices accessed with a too high SPI clock.The remaining patches improve the performance of the driver. The changes range
from micro-optimizations like reducing MMIO writes to the controller to
reducing the number of needed interrupts in some use cases.regards,
Marcchanges since v1:
- added Maxime Ripard's to the existing patches
- 06/10: (was 05/10 in v1)
"spi: spi-sun6i: sun6i_spi_drain_fifo(): introduce sun6i_spi_get_rx_fifo_count() and make use of it"
use FIELD_GET instead of open coding it
(tnx: Maxime Ripard)
- 05/10: "spi: spi-sun6i: sun6i_spi_get_tx_fifo_count: Convert manual shift+mask to FIELD_GET()"
new patch_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
25 Jun, 2020
1 commit
-
Add Intel Tiger Lake PCH-H PCI IDs.
Signed-off-by: Jarkko Nikula
Link: https://lore.kernel.org/r/20200625140041.745804-1-jarkko.nikula@linux.intel.com
Signed-off-by: Mark Brown
30 May, 2020
1 commit
26 May, 2020
2 commits
-
The PXA2xx SPI driver releases a runtime PM ref in the probe error path
even though it hasn't acquired a ref earlier.Apparently commit e2b714afee32 ("spi: pxa2xx: Disable runtime PM if
controller registration fails") sought to copy-paste the invocation of
pm_runtime_disable() from pxa2xx_spi_remove(), but erroneously copied
the call to pm_runtime_put_noidle() as well. Drop it.Fixes: e2b714afee32 ("spi: pxa2xx: Disable runtime PM if controller registration fails")
Signed-off-by: Lukas Wunner
Reviewed-by: Jarkko Nikula
Reviewed-by: Andy Shevchenko
Cc: stable@vger.kernel.org # v4.17+
Cc: Jarkko Nikula
Link: https://lore.kernel.org/r/58b2ac6942ca1f91aaeeafe512144bc5343e1d84.1590408496.git.lukas@wunner.de
Signed-off-by: Mark Brown -
The PXA2xx SPI driver uses devm_spi_register_controller() on bind.
As a consequence, on unbind, __device_release_driver() first invokes
pxa2xx_spi_remove() before unregistering the SPI controller via
devres_release_all().This order is incorrect: pxa2xx_spi_remove() disables the chip,
rendering the SPI bus inaccessible even though the SPI controller is
still registered. When the SPI controller is subsequently unregistered,
it unbinds all its slave devices. Because their drivers cannot access
the SPI bus, e.g. to quiesce interrupts, the slave devices may be left
in an improper state.As a rule, devm_spi_register_controller() must not be used if the
->remove() hook performs teardown steps which shall be performed after
unregistering the controller and specifically after unbinding of slaves.Fix by reverting to the non-devm variant of spi_register_controller().
An alternative approach would be to use device-managed functions for all
steps in pxa2xx_spi_remove(), e.g. by calling devm_add_action_or_reset()
on probe. However that approach would add more LoC to the driver and
it wouldn't lend itself as well to backporting to stable.The improper use of devm_spi_register_controller() was introduced in 2013
by commit a807fcd090d6 ("spi: pxa2xx: use devm_spi_register_master()"),
but all earlier versions of the driver going back to 2006 were likewise
broken because they invoked spi_unregister_master() at the end of
pxa2xx_spi_remove(), rather than at the beginning.Fixes: e0c9905e87ac ("[PATCH] SPI: add PXA2xx SSP SPI Driver")
Signed-off-by: Lukas Wunner
Reviewed-by: Andy Shevchenko
Cc: stable@vger.kernel.org # v2.6.17+
Cc: Tsuchiya Yuto
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206403#c1
Link: https://lore.kernel.org/r/834c446b1cf3284d2660f1bee1ebe3e737cd02a9.1590408496.git.lukas@wunner.de
Signed-off-by: Mark Brown
30 Apr, 2020
1 commit
-
With a couple allies at Intel, and much badgering, I got confirmation
from Intel that at least BXT suffers from the same SPI chip-select
issue as Cannonlake (and beyond). The issue being that after going
through runtime suspend/resume, toggling the chip-select line without
also sending data does nothing.Add the quirk to BXT to briefly toggle dynamic clock gating off and
on, forcing the fabric to wake up enough to notice the CS register
change.Signed-off-by: Evan Green
Cc: Shobhit Srivastava
Cc: Andy Shevchenko
Link: https://lore.kernel.org/r/20200427163238.1.Ib1faaabe236e37ea73be9b8dcc6aa034cb3c8804@changeid
Signed-off-by: Mark Brown
02 Mar, 2020
1 commit
-
…andr.suvorov@toradex.com>:
- fix the values source for the xfer debug message.
- fix the "max speed setting" message showing.Oleksandr Suvorov (2):
spi: spidev: fix a debug message value
spi: spidev: fix speed setting messagedrivers/spi/spidev.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)--
2.24.1
29 Feb, 2020
1 commit
-
Introduce is_mmp2_ssp() helper to be consistent with the rest
helper function to distinguish SSP type.Signed-off-by: Andy Shevchenko
Link: https://lore.kernel.org/r/20200227162556.3152-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown
27 Feb, 2020
1 commit
-
In some circumstances on Intel LPSS controllers, toggling the LPSS
CS control register doesn't actually cause the CS line to toggle.
This seems to be failure of dynamic clock gating that occurs after
going through a suspend/resume transition, where the controller
is sent through a reset transition. This ruins SPI transactions
that either rely on delay_usecs, or toggle the CS line without
sending data.Whenever CS is toggled, momentarily set the clock gating register
to "Force On" to poke the controller into acting on CS.Signed-off-by: Rajat Jain
Signed-off-by: Evan Green
Link: https://lore.kernel.org/r/20200211223700.110252-1-rajatja@google.com
Signed-off-by: Mark Brown
25 Feb, 2020
2 commits
-
There is no need for drv_data check against NULL, since it won't happen.
Remove useless check.Signed-off-by: Andy Shevchenko
Link: https://lore.kernel.org/r/20200224154556.11627-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown -
For better understanding what's going on on error path,
return distinguished error codes instead of NULL pointer.Signed-off-by: Andy Shevchenko
Link: https://lore.kernel.org/r/20200224154556.11627-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown
23 Jan, 2020
1 commit
22 Jan, 2020
1 commit
-
A read from a Winbond W25Q32FV SPI NOR memory chip on my MMP2 returns
wrong data.It seems like SSE doesn't do the right thing on MMP2 at all. After
enabling the SPI port back again, the FIFO reads return garbage. Things
can be brought back to order by telling the PMU to reset the block.Here's a good transaction with said chip:
# busybox devmem 0xd4035000 32 0x00001987 # SSCR0
# echo 0 >/sys/class/gpio/gpio46/value # (assert CS)
# busybox devmem 0xd4035010 32 0x0000009f # SSDR (read ID command)
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 # SSDR
0x000000ff
# busybox devmem 0xd4035010 # SSDR
0x000000ef # Correct response
# busybox devmem 0xd4035010 # SSDR
0x00000040
# busybox devmem 0xd4035010 # SSDR
0x00000016
# busybox devmem 0xd4035010 # SSDR
0x00000000
# busybox devmem 0xd4035010 # SSDR
0x00000000
# busybox devmem 0xd4035010 # SSDR
0x00000000
# echo 1 >/sys/class/gpio/gpio46/value # (deassert CS)
#Flipping off an on SSE, then running another transaction:
# busybox devmem 0xd4035000 32 0x00001907 # SSCR0, SSE off
# busybox devmem 0xd4035000 32 0x00001987 # SSCR0, SSE on
# echo 0 >/sys/class/gpio/gpio46/value # (assert CS)
# busybox devmem 0xd4035010 32 0x0000009f # SSDR (read ID command)
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 # SSDR
0x000000ff
# busybox devmem 0xd4035010 # SSDR
0x000000ff # Garbage!
# busybox devmem 0xd4035010 # SSDR
0x000000ff # Oh no
# busybox devmem 0xd4035010 # SSDR
0x000000ff
# busybox devmem 0xd4035010 # SSDR
0x000000ff
# busybox devmem 0xd4035010 # SSDR
0x000000ff
# busybox devmem 0xd4035010 # SSDR
0x000000ff
# echo 1 >/sys/class/gpio/gpio46/value # (deassert CS)
#Sometimes the response is not just ones, but something that looks like
bits of a response from a previous transaction.I can't see a fix other than not touching the SSE altogether after the
device is first brought up.Signed-off-by: Lubomir Rintel
Link: https://lore.kernel.org/r/20200118094031.327373-1-lkundrak@v3.sk
Signed-off-by: Mark Brown
17 Jan, 2020
1 commit
-
Add support for Intel Comet Lake PCH-V which has the same LPSS than on
Intel Kaby lake unlike other Intel Comet Lake PCH variants that are based
on Intel Cannon Lake PCH LPSS.Signed-off-by: Jarkko Nikula
Link: https://lore.kernel.org/r/20200116091035.575175-1-jarkko.nikula@linux.intel.com
Signed-off-by: Mark Brown
26 Dec, 2019
1 commit
18 Dec, 2019
1 commit
-
Pull spi fixes from Mark Brown:
"A relatively large set of fixes here, the biggest part of it is for
fallout from the GPIO descriptor rework that affected several of the
devices with usable native chip select support. There's also some new
PCI IDs for Intel Jasper Lake devices.The conversion to platform_get_irq() in the fsl driver is an
incremental fix for build errors introduced on SPARC by the earlier
fix for error handling in probe in that driver"* tag 'spi-fix-v5.5-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: fsl: use platform_get_irq() instead of of_irq_to_resource()
spi: nxp-fspi: Ensure width is respected in spi-mem operations
spi: spi-ti-qspi: Fix a bug when accessing non default CS
spi: fsl: don't map irq during probe
spi: spi-cavium-thunderx: Add missing pci_release_regions()
spi: sprd: Fix the incorrect SPI register
gpiolib: of: Make of_gpio_spi_cs_get_count static
spi: fsl: Handle the single hardwired chipselect case
gpio: Handle counting of Freescale chipselects
spi: fsl: Fix GPIO descriptor support
spi: dw: Correct handling of native chipselect
spi: cadence: Correct handling of native chipselect
spi: pxa2xx: Add support for Intel Jasper Lake
25 Nov, 2019
1 commit
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LPSS SPI on Intel Jasper Lake is compatible with Intel Ice Lake which
follows Intel Cannon Lake. Add PCI IDs of Jasper Lake.Signed-off-by: Jarkko Nikula
Link: https://lore.kernel.org/r/20191125125159.15404-1-jarkko.nikula@linux.intel.com
Signed-off-by: Mark Brown
23 Nov, 2019
1 commit
11 Nov, 2019
1 commit
-
pxa2xx_spi_init_pdata misses checks for devm_clk_get and
platform_get_irq.
Add checks for them to fix the bugs.Since ssp->clk and ssp->irq are used in probe, they are mandatory here.
So we cannot use _optional() for devm_clk_get and platform_get_irq.Signed-off-by: Chuhong Yuan
Link: https://lore.kernel.org/r/20191109080943.30428-1-hslester96@gmail.com
Signed-off-by: Mark Brown
29 Oct, 2019
1 commit
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Add Intel Comet Lake-H LPSS SPI PCI IDs.
Signed-off-by: Jarkko Nikula
Link: https://lore.kernel.org/r/20191029115802.6779-1-jarkko.nikula@linux.intel.com
Signed-off-by: Mark Brown
25 Oct, 2019
1 commit
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The current conditional for PCI ID matching is hard to read.
Introduce couple of temporary variables to increase readability
of the code.Signed-off-by: Andy Shevchenko
Link: https://lore.kernel.org/r/20191021103625.4250-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown
24 Oct, 2019
1 commit
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The devm_ioremap_resource() has already a check for resource pointer
being NULL. No need to double check this.Drop extra check of platform_get_resource() returned value.
Signed-off-by: Andy Shevchenko
Link: https://lore.kernel.org/r/20191021103625.4250-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown
19 Oct, 2019
6 commits
-
There is nothing in use from of_device.h. The definitions and macros
are available thru mod_devicetable.h and of.h.Signed-off-by: Andy Shevchenko
Link: https://lore.kernel.org/r/20191018105429.82782-5-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown -
Convert to use device_get_match_data() instead of open coded variant.
While here, switch of_property_read_bool() to device_property_read_bool().
Signed-off-by: Andy Shevchenko
Link: https://lore.kernel.org/r/20191018105429.82782-4-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown -
This is preparatory patch before converting to use device_get_match_data() API.
Signed-off-by: Andy Shevchenko
Link: https://lore.kernel.org/r/20191018105429.82782-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown -
Sort the headers in alphabetic order in order to ease the maintenance
for this part.Signed-off-by: Andy Shevchenko
Link: https://lore.kernel.org/r/20191018105429.82782-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown -
There is no need to keep a pointer to the platform device. Currently there are
no users of it directly, and if there will be in the future we may restore it
from pointer to the struct device.Convert all users at the same time.
Cc: Russell King
Cc: Jaroslav Kysela
Cc: Takashi Iwai
Signed-off-by: Andy Shevchenko
Link: https://lore.kernel.org/r/20191018105429.82782-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown -
In DMA mode we have a maximum transfer size, past that the driver
falls back to PIO (see the check at the top of pxa2xx_spi_transfer_one).
Falling back to PIO for big transfers defeats the point of a dma engine,
hence set the max transfer size to inform spi clients that they need
to do something smarter.This was uncovered by the drm_mipi_dbi spi panel code, which does
large spi transfers, but stopped splitting them after:commit e143364b4c1774f68e923a5a0bb0fca28ac25888
Author: Noralf Trønnes
Date: Fri Jul 19 17:59:10 2019 +0200drm/tinydrm: Remove tinydrm_spi_max_transfer_size()
After this commit the code relied on the spi core to split transfers
into max dma-able blocks, which also papered over the PIO fallback issue.Fix this by setting the overall max transfer size to the DMA limit,
but only when the controller runs in DMA mode.Fixes: e143364b4c17 ("drm/tinydrm: Remove tinydrm_spi_max_transfer_size()")
Cc: Sam Ravnborg
Cc: Noralf Trønnes
Cc: Andy Shevchenko
Reported-and-tested-by: Andy Shevchenko
Cc: Daniel Mack
Cc: Haojian Zhuang
Cc: Robert Jarzmik
Cc: Mark Brown
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-spi@vger.kernel.org
Signed-off-by: Daniel Vetter
Link: https://lore.kernel.org/r/20191017064426.30814-1-daniel.vetter@ffwll.ch
Signed-off-by: Mark Brown
02 Aug, 2019
1 commit
-
Intel Tiger Lake -LP LPSS SPI controller is otherwise similar than
Cannon Lake but has more controllers and up to two chip selects per
controller.Signed-off-by: Jarkko Nikula
Link: https://lore.kernel.org/r/20190801134901.12635-1-jarkko.nikula@linux.intel.com
Signed-off-by: Mark Brown
22 Jul, 2019
1 commit
-
Don't undo the PM initialization if we error out before we managed to
initialize it. The call to pm_runtime_disable() without being preceded
by pm_runtime_enable() would disturb the balance of the Force.In practice, this happens if we fail to allocate any of the GPIOS ("cs",
"ready") due to -EPROBE_DEFER because we're getting probled before the
GPIO driver.Signed-off-by: Lubomir Rintel
Link: https://lore.kernel.org/r/20190719122713.3444318-1-lkundrak@v3.sk
Signed-off-by: Mark Brown
03 Jul, 2019
1 commit
-
Intel Elkhart Lake has the same LPSS than Intel Broxton. Add support for
it.Signed-off-by: Jarkko Nikula
Link: https://lore.kernel.org/r/20190703114603.22301-1-jarkko.nikula@linux.intel.com
Signed-off-by: Mark Brown
02 Jul, 2019
1 commit
-
It is possible to request a transfer with a speed lower than supported
by the HW. This causes silent divider calculation underflow in
ssp_get_clk_div() which leads to a frequency higher than requested. Up to
maximum speed of the controller.Set the minimum supported transfer speed and let the SPI core to
validate no transfers have speed lower than supported.Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
31 May, 2019
1 commit
-
Based on 3 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version this program is distributed in the
hope that it will be useful but without any warranty without even
the implied warranty of merchantability or fitness for a particular
purpose see the gnu general public license for more detailsthis program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version [author] [kishon] [vijay] [abraham]
[i] [kishon]@[ti] [com] this program is distributed in the hope that
it will be useful but without any warranty without even the implied
warranty of merchantability or fitness for a particular purpose see
the gnu general public license for more detailsthis program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version [author] [graeme] [gregory]
[gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i]
[kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema]
[hk] [hemahk]@[ti] [com] this program is distributed in the hope
that it will be useful but without any warranty without even the
implied warranty of merchantability or fitness for a particular
purpose see the gnu general public license for more detailsextracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 1105 file(s).
Signed-off-by: Thomas Gleixner
Reviewed-by: Allison Randal
Reviewed-by: Richard Fontana
Reviewed-by: Kate Stewart
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de
Signed-off-by: Greg Kroah-Hartman
09 May, 2019
1 commit
-
Pull dmaengine updates from Vinod Koul:
- Updates to stm32 dma residue calculations
- Interleave dma capability to axi-dmac and support for ZynqMP arch
- Rework of channel assignment for rcar dma
- Debugfs for pl330 driver
- Support for Tegra186/Tegra194, refactoring for new chips and support
for pause/resume- Updates to axi-dmac, bcm2835, fsl-edma, idma64, imx-sdma, rcar-dmac,
stm32-dma etc- dev_get_drvdata() updates on few drivers
* tag 'dmaengine-5.2-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (34 commits)
dmaengine: tegra210-adma: restore channel status
dmaengine: tegra210-dma: free dma controller in remove()
dmaengine: tegra210-adma: add pause/resume support
dmaengine: tegra210-adma: add support for Tegra186/Tegra194
Documentation: DT: Add compatibility binding for Tegra186
dmaengine: tegra210-adma: prepare for supporting newer Tegra chips
dmaengine: at_xdmac: remove a stray bottom half unlock
dmaengine: fsl-edma: Adjust indentation
dmaengine: fsl-edma: Fix typo in Vybrid name
dmaengine: stm32-dma: fix residue calculation in stm32-dma
dmaengine: nbpfaxi: Use dev_get_drvdata()
dmaengine: bcm-sba-raid: Use dev_get_drvdata()
dmaengine: stm32-dma: Fix unsigned variable compared with zero
dmaengine: stm32-dma: use platform_get_irq()
dmaengine: rcar-dmac: Update copyright information
dmaengine: imx-sdma: Only check ratio on parts that support 1:1
dmaengine: xgene-dma: fix spelling mistake "descripto" -> "descriptor"
dmaengine: idma64: Move driver name to the header
dmaengine: bcm2835: Drop duplicate capability setting.
dmaengine: pl330: _stop: clear interrupt status
...
02 May, 2019
4 commits
-
Calculate the divisor for the SCR (Serial Clock Rate), avoiding
that the SSP transmission rate can be greater than the device rate.When the division between the SSP clock and the device rate generates
a reminder, we have to increment by one the divisor.
In this way the resulting SSP clock will never be greater than the
device SPI max frequency.For example, with:
- ssp_clk = 50 MHz
- dev freq = 15 MHzwithout this patch the SSP clock will be greater than 15 MHz:
- 25 MHz for PXA25x_SSP and CE4100_SSP
- 16,56 MHz for the othersInstead, with this patch, we have in both case an SSP clock of 12.5MHz,
so the max rate of the SPI device clock is respected.Signed-off-by: Flavio Suligoi
Reviewed-by: Jarkko Nikula
Reviewed-by: Jarkko Nikula
Signed-off-by: Mark Brown -
Add PCI IDs for SPI on Comet Lake.
Signed-off-by: Evan Green
Acked-by: Andy Shevchenko
Reviewed-by: Jarkko Nikula
Signed-off-by: Mark Brown -
With dw_dmac, sometimes the request of a DMA channel fails because
the DMA driver is not ready, so an explicit dependency request
is necessary.Signed-off-by: Flavio Suligoi
Signed-off-by: Mark Brown
