15 Jul, 2016
1 commit
-
Install the callbacks via the state machine and let the core invoke
the callbacks on the already online CPUs.Signed-off-by: Richard Cochran
Signed-off-by: Anna-Maria Gleixner
Reviewed-by: Sebastian Andrzej Siewior
Acked-by: Ralf Baechle
Cc: Linus Torvalds
Cc: Peter Zijlstra
Cc: Robert Richter
Cc: Thomas Gleixner
Cc: linux-mips@linux-mips.org
Cc: oprofile-list@lists.sf.net
Cc: rt@linutronix.de
Link: http://lkml.kernel.org/r/20160713153337.054827168@linutronix.de
Signed-off-by: Ingo Molnar
28 May, 2016
1 commit
-
Signed-off-by: Andrea Gelmini
Cc: rric@kernel.org
Cc: linux-mips@linux-mips.org
Cc: trivial@kernel.org
Cc: oprofile-list@lists.sf.net
Patchwork: https://patchwork.linux-mips.org/patch/13334/
Signed-off-by: Ralf Baechle
13 May, 2016
1 commit
-
Add CPU feature for standard MIPS r2 performance counters, as determined
by the Config1.PC bit. Both perf_events and oprofile probe this bit, so
lets combine the probing and change both to use cpu_has_perf.This will also be used for VZ support in KVM to know whether performance
counters exist which can be exposed to guests.[ralf@linux-mips.org: resolve conflict.]
Signed-off-by: James Hogan
Cc: Peter Zijlstra
Cc: Ingo Molnar
Cc: Arnaldo Carvalho de Melo
Cc: Alexander Shishkin
Cc: Robert Richter
Cc: linux-mips@linux-mips.org
Cc: oprofile-list@lists.sf.net
Patchwork: https://patchwork.linux-mips.org/patch/13226/
Signed-off-by: Ralf Baechle
09 May, 2016
1 commit
-
Use boot_cpu_type() instead of current_cpu_type() in oprofile_arch_init()
to avoid the below warning, cpu_type is normally consistent in a MIPS SMP
system. There are a few exceptions such as SGI servers where it is
possible to mix R10000, R12000, R14000 and R16000 within certain
constraints. Let's not worry about those now.BUG: using smp_processor_id() in preemptible [00000000] code: insmod/952
caller is oprofile_arch_init+0x30/0x194 [oprofile]
CPU: 5 PID: 952 Comm: insmod Not tainted 4.1.13-WR8.0.0.0_standard #1
Stack : ffffffff80c10000 0000000000000001 8000000025bf0790 ffffffff80e10000
ffffffff80e50000 ffffffff80254e2c ffffffff80b64428 ffffffff80e10790
0000000000000000 ffffffff801caeb8 0000000000000045 0000000000000005
ffffffff80c10000 ffffffff801cb798 0000000000000000 ffffffff80e30000
0000000000000000 ffffffff801ff1c0 ffffffff80e2d2f8 000000000000000b
ffffffff801cbba0 ffffffff80e107b0 ffffffff80a77828 0000000000000005
00000000000003b8 ffffffff80e2d2f8 800000040ad39960 ffffffff801f9950
0000000000000124 80000004093b7990 80000004093b7ab8 ffffffff80925108
ffffffff80b69a07 ffffffff80a6f0d0 8000000407240e00 ffffffff801cc934
000000000000005d ffffffff80159080 0000000000000005 00000000000003b8
...
Call Trace:
[] show_stack+0xe8/0x108
[] dump_stack+0x8c/0xd8
[] check_preemption_disabled+0x110/0x118
[] oprofile_arch_init+0x30/0x194 [oprofile]
[] oprofile_init+0x2c/0xc0 [oprofile]
[] do_one_initcall+0xa0/0x1c0
[] do_init_module+0x80/0x1d8
[] load_module+0x1b74/0x2278
[] SyS_finit_module+0xcc/0xf0
[] handle_sysn32+0x44/0x70[ralf@linux-mips.org: Correct commit message.]
Signed-off-by: Yanjiang Jin
Cc: rric@kernel.org
Cc: jinyanjiang@gmail.com
Cc: linux-mips@linux-mips.org
Cc: oprofile-list@lists.sf.net
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11769/
Signed-off-by: Ralf Baechle
26 Aug, 2015
1 commit
-
Add a CPU_I6400 case to various switch statements, doing the same thing
as for CPU_P5600.Signed-off-by: Markos Chandras
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10635/
Signed-off-by: Ralf Baechle
01 Apr, 2015
1 commit
-
This allows the kernel to correctly detect an R16000 MIPS CPU on systems that
have those. Otherwise, such systems will detect the CPU as an R14000, due to
similarities in the CPU PRId value.Signed-off-by: Joshua Kinard
Cc: Linux MIPS List
Patchwork: https://patchwork.linux-mips.org/patch/9092/
Signed-off-by: Ralf Baechle
31 Mar, 2015
3 commits
-
When requesting the performance counter overflow interrupt, pass flags
which are compatible with the cevt-r4k driver, in particular
IRQF_SHARED so that the two handlers can share the same IRQ. This is
possible since release 2 of the architecture where there are separate
pending interrupt bits for the timer interrupt and the performance
counter interrupt.This will be necessary since the FDC interrupt can also be arbitrarily
routed to a CPU interrupt, possibly sharing with the timer, the
performance counters, or both, and it isn't scalable to have all the
handlers able to call other handlers that may be on the same IRQ line.Signed-off-by: James Hogan
Cc: Robert Richter
Cc: linux-mips@linux-mips.org
Cc: oprofile-list@lists.sf.net
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9130/
Signed-off-by: Ralf Baechle -
The situation where the timer interrupt is on the same line as the
performance counter interrupt is handled in per_cpu_trap_init() by
setting cp0_perfcount_irq to -1, so there is no need to duplicate the
logic conditional upon cp0_perfcount_irq >= 0 in perf
(init_hw_perf_events()) and oprofile (mipsxx_init()).Signed-off-by: James Hogan
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9125/
Signed-off-by: Ralf Baechle -
Use CAUSEF_TI and CAUSEF_PCI constants from asm/mipsregs.h rather than
the magic values (1 << 30) and (1 << 26).Signed-off-by: James Hogan
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9124/
Signed-off-by: Ralf Baechle
24 Nov, 2014
4 commits
-
Continue the backtrace if we cannot find SP adjustment and RA save. In
that case, just assume the current RA. This allows us to get samples of
frequent callers of e.g. GLIBC memset().Signed-off-by: Aaro Koskinen
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8109/
Signed-off-by: Ralf Baechle -
Allow unsupported CPU types to use backtrace with timer-based profiling.
Some CPUs (notably OCTEON) lack architecture-specific oprofile driver. In
such case oprofile can fallback to timer-based mode, and arch code can
still provide the backtrace functionality. So just set up the backtrace
hook always.Signed-off-by: Aaro Koskinen
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8108/
Signed-off-by: Ralf Baechle -
Loongson-3 has two groups of performance counters, they are 4 sub-
registers of CP0's REG25. This patch add oprofile support.REG25, sel 0: Perf Control of group 0;
REG25, sel 1: Perf Counter of group 0;
REG25, sel 2: Perf Control of group 1;
REG25, sel 3: Perf Counter of group 1.Signed-off-by: Huacai Chen
Cc: John Crispin
Cc: Steven J. Hill
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Patchwork: https://patchwork.linux-mips.org/patch/8328/
Signed-off-by: Ralf Baechle -
The hardware perf event driver and oprofile interpret the global
cp0_perfcount_irq differently: in the hardware perf event driver
it is an offset from MIPS_CPU_IRQ_BASE and in oprofile it is the
actual IRQ number. This still works most of the time since
MIPS_CPU_IRQ_BASE is usually 0, but is clearly wrong. Since the
performance counter interrupt may vary from platform to platform
like the C0 timer interrupt, add the optional get_c0_perfcount_int
hook which returns the IRQ number of the performance counter.
The hook should return < 0 if the performance counter interrupt is
shared with the timer. If the hook is not present, the CPU vector
reported in C0_IntCtl (cp0_perfcount_irq) is used.Signed-off-by: Andrew Bresticker
Reviewed-by: Qais Yousef
Tested-by: Qais Yousef
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Andrew Bresticker
Cc: Jeffrey Deans
Cc: Markos Chandras
Cc: Paul Burton
Cc: Qais Yousef
Cc: Jonas Gorski
Cc: John Crispin
Cc: David Daney
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7805/
Signed-off-by: Ralf Baechle
20 Nov, 2014
1 commit
-
Fix incorrect cast that always results in wrong address for the new
frame on 64-bit kernels.Signed-off-by: Aaro Koskinen
Cc: stable@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8110/
Signed-off-by: Ralf Baechle
27 Mar, 2014
2 commits
-
The M5150 core is a 32-bit MIPS RISC which implements the
MIPS Architecture Release-5 in a 5-stage pipeline.
In addition, it includes the MIPS Architecture Virtualization Module
that enables virtualization of operating systems,
which provides a scalable, trusted, and secure execution environment.Signed-off-by: Leonid Yegoshin
Signed-off-by: Markos Chandras
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6596/
Signed-off-by: Ralf Baechle -
Add a CPU_P5600 cpu type case in oprofile_arch_init() to use the MIPS
model, and in mipsxx_init() to set the cpu_type string to "mips/P5600".Signed-off-by: James Hogan
Reviewed-by: Markos Chandras
Cc: linux-mips@linux-mips.org
Cc: Robert Richter
Cc: oprofile-list@lists.sf.net
Patchwork: https://patchwork.linux-mips.org/patch/6410/
Signed-off-by: Ralf Baechle
07 Mar, 2014
1 commit
-
The 1074K is a multiprocessing coherent processing system (CPS) based
on modified 74K cores. This patch makes the 1074K an actual unique
CPU type, instead of a 74K derivative, which it is not.Signed-off-by: Steven J. Hill
Reviewed-by: Leonid Yegoshin
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6389/
Signed-off-by: Ralf Baechle
23 Jan, 2014
2 commits
-
The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit.Signed-off-by: Leonid Yegoshin
Signed-off-by: Markos Chandras
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6163/ -
The proAptiv Multiprocessing System is a power efficient multi-core
microprocessor for use in system-on-chip (SoC) applications.
The proAptiv Multiprocessing System combines a deep pipeline
with multi-issue out of order execution for improved computational
throughput. The proAptiv Multiprocessing System can contain one to
six MIPS32r3 proAptiv cores, system level coherence
manager with L2 cache, optional coherent I/O port, and optional
floating point unit.Signed-off-by: Leonid Yegoshin
Signed-off-by: Markos Chandras
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6134/
18 Sep, 2013
1 commit
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o Move current_cpu_type() to a separate header file
o #ifdefing on supported CPU types lets modern GCC know that certain
code in callers may be discarded ideally turning current_cpu_type() into
a function returning a constant.
o Use current_cpu_type() rather than direct access to struct cpuinfo_mips.Signed-off-by: Ralf Baechle
Cc: Steven J. Hill
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5833/
04 Sep, 2013
3 commits
-
same story as with oprofilefs_mkdir()
Signed-off-by: Al Viro
-
it's always equal to ->d_sb of the second argument (parent dentry),
due to either being literally that, or ->d_sb of parent's parent.Signed-off-by: Al Viro
-
Signed-off-by: Al Viro
05 Aug, 2013
1 commit
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current_cpu_type() is not preemption-safe.
If CONFIG_PREEMPT is enabled then mipsxx_reg_setup() can be called from preemptible state.
Added get_cpu()/put_cpu() pair to make it preemption-safe.This was found while testing oprofile with CONFIG_DEBUG_PREEMPT enable.
/usr/zntestsuite # opcontrol --init
/usr/zntestsuite # opcontrol --setup --event=L2_CACHE_ACCESSES:500 --event=L2_CACHE_MISSES:500 --no-vmlinux
/usr/zntestsuite # opcontrol --start
Using 2.6+ OProfile kernel interface.
BUG: using smp_processor_id() in preemptible [00000000] code: oprofiled/1362
caller is mipsxx_reg_setup+0x11c/0x164
CPU: 0 PID: 1362 Comm: oprofiled Not tainted 3.10.4 #18
Stack : 00000006 70757465 00000000 00000000 00000000 00000000 80b173f6 00000037
80b10000 00000000 80b21614 88f5a220 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 89c49c00 89c49c2c 80721254 807b7927 8012c1d0
80b10000 80721254 00000000 00000552 88f5a220 80b1335c 807b78e6 89c49ba8
...
Call Trace:
[] show_stack+0x64/0x7c
[] dump_stack+0x20/0x2c
[] debug_smp_processor_id+0xe0/0xf0
[] mipsxx_reg_setup+0x11c/0x164
[] op_mips_setup+0x24/0x4c
[] oprofile_setup+0x5c/0x12c
[] event_buffer_open+0x78/0xf8
[] do_dentry_open.isra.15+0x2b8/0x3b0
[] finish_open+0x28/0x4c
[] do_last.isra.41+0x2cc/0xd00
[] path_openat+0xb4/0x4c4
[] do_filp_open+0x3c/0xac
[] do_sys_open+0x110/0x1f4
[] stack_done+0x20/0x44Bug reported and original patch by Jerin Jacob .
Signed-off-by: Ralf Baechle
Acked-by: Jerin Jacob
08 May, 2013
1 commit
-
The commit c783390a0ecef08df5c804f8c5f647431a04f502 [MIPS: oprofile:
Support for XLR/XLS processors] causes a compilation failure when
oprofile is enabled and SMP is not configured.arch/mips/oprofile/op_model_mipsxx.c: In function 'mipsxx_cpu_setup':
arch/mips/oprofile/op_model_mipsxx.c:181:2: error: implicit declaration of function 'cpu_logical_map'To fix this, update oprofile_skip_cpu to not call cpu_logical_map when
CONFIG_SMP is not defined.Signed-off-by: Jayachandran C
Patchwork: http://patchwork.linux-mips.org/patch/5037/
Acked-by: John Crispin
21 Feb, 2013
1 commit
-
… into mips-for-linux-next
17 Feb, 2013
1 commit
-
Signed-off-by: Steven J. Hill
Patchwork: http://patchwork.linux-mips.org/patch/4682/
Signed-off-by: John Crispin
01 Feb, 2013
1 commit
-
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.Signed-off-by: Ralf Baechle
14 Dec, 2012
2 commits
-
Nobody seems to be interested anymore and upstream also never had an
ethernet driver.Signed-off-by: Ralf Baechle
09 Nov, 2012
1 commit
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Add support for XLR and XLS processors in MIPS Oprofile code. These
processors are multi-threaded and have two counters per core. Each
counter can track either all the events in the core (global mode),
or events in just one thread.We use the counters in the global mode, and use only the first thread
in each core to handle the configuration etc.Signed-off-by: Madhusudan Bhat
Signed-off-by: Jayachandran C
Patchwork: http://patchwork.linux-mips.org/patch/4471
Signed-off-by: John Crispin
25 Jul, 2012
1 commit
-
…ext/jz4740', 'next/lantiq', 'next/loongson1b' and 'next/netlogic' into mips-for-linux-next
23 Jul, 2012
2 commits
-
Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology
(ICT) and the Chinese Academy of Sciences (CAS), which implements the
MIPS32 release 2 instruction set.[ralf@linux-mips.org: But which is not strictly a MIPS32 compliant device
which also is why it identifies itself with the Legacy Vendor ID in the
PrID register. When applying the patch I shoveled some code around to
keep things in alphabetical order and avoid forward declarations.]Signed-off-by: Kelvin Cheung
Cc: To: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: wuzhangjin@gmail.com
Cc: zhzhl555@gmail.com
Cc: Kelvin Cheung
Patchwork: https://patchwork.linux-mips.org/patch/3976/
Signed-off-by: Ralf Baechle -
Signed-off-by: Steven J. Hill
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3854/
Signed-off-by: Ralf Baechle
07 Jul, 2012
1 commit
-
[ralf@linux-mips.org: Fixed whitespace damage.]
Signed-off-by: Steven J. Hill
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3773/
Signed-off-by: Ralf Baechle
27 May, 2012
1 commit
-
…th79' and 'next/lantiq' into mips-for-linux-next
21 May, 2012
1 commit
-
Signed-off-by: Ralf Baechle
15 May, 2012
1 commit
-
Make the oprofile code use the performance counters irq.
Signed-off-by: Felix Fietkau
Signed-off-by: John Crispin
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3723/
Signed-off-by: Ralf Baechle
15 Jun, 2011
1 commit
-
Stack unwinding is done by code examination. For kernelspace, the
already existing unwind function is utilized that uses kallsyms to
quickly find the beginning of functions. For userspace a new function
was added that examines code at and before the pc.Signed-off-by: Daniel Kalmar
Signed-off-by: Gergely Kis
Signed-off-by: Robert Richter
17 Mar, 2011
1 commit
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Replace EXTRA_CFLAGS with ccflags-y.
Signed-off-by: matt mooney
Acked-by: WANG Cong
Signed-off-by: Michal Marek
