15 Jul, 2019
2 commits
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Now that several arch documents were converted to ReST,
add their indexes to Documentation/index.rst and remove the
:orphan: from them.Signed-off-by: Mauro Carvalho Chehab
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Rename the xtensa documentation files to ReST, add an
index for them and adjust in order to produce a nice html
output via the Sphinx build system.At its new index.rst, let's add a :orphan: while this is not linked to
the main index.rst file, in order to avoid build warnings.Signed-off-by: Mauro Carvalho Chehab
04 Feb, 2019
1 commit
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Add booting.txt to Documentation/xtensa with description of boot
parameters representation and passing to the kernel.Signed-off-by: Max Filippov
17 Dec, 2017
2 commits
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Cover kernel addresses above 0x90000000 by the shadow map. Enable
HAVE_ARCH_KASAN when MMU is enabled. Provide kasan_early_init that fills
shadow map with writable copies of kasan_zero_page. Call
kasan_early_init right after mmu initialization in the setup_arch.
Provide kasan_init that allocates proper shadow map pages from the
memblock and puts these pages into the shadow map for addresses from
VMALLOC area to the end of KSEG. Call kasan_init right after memblock
initialization. Don't use KASAN for the boot code, MMU and KASAN
initialization and page fault handler. Make kernel stack size 4 times
larger when KASAN is enabled to avoid stack overflows.
GCC 7.3, 8 or newer is required to build the xtensa kernel with KASAN.Signed-off-by: Max Filippov
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The virtual address space between the page table and the VMALLOC region
is big enough to host KASAN shadow map and there's enough space between
the VMALLOC area and KSEG for the fixmap and kmap.
Move fixmap and kmap to the gap between VMALLOC area and KSEG, just
above the KSEG. Reorder entries in the kernel memory layout printing
code. Drop duplicate PGTABLE_START definition, use
XCHAL_PAGE_TABLE_VADDR instead.Signed-off-by: Max Filippov
23 Jun, 2017
1 commit
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The Devicetree Specification has superseded the ePAPR as the
base specification for bindings. Update files in Documentation
to reference the new document.First reference to ePAPR in Documentation/devicetree/bindings/arm/cci.txt
is generic, remove it.Some files are not updated because there is no hypervisor chapter
in the Devicetree Specification:
Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
Documenation/virtual/kvm/api.txt
Documenation/virtual/kvm/ppc-pv.txtSigned-off-by: Frank Rowand
Signed-off-by: Rob Herring
24 Jul, 2016
2 commits
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Make kernel load address explicit, independent of the selected MMU
configuration and configurable from Kconfig. Do not restrict it to the
first 512MB of the physical address space.Cleanup kernel memory layout macros:
- rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR;
- drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS;
- introduce PHYS_OFFSET and use it in __va and __pa definitions;
- synchronize MMU/noMMU vectors, drop unused NMI vector;
- replace hardcoded vectors offset of 0x3000 with Kconfig symbol.Signed-off-by: Max Filippov
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MMUv3 is able to support low memory bigger than 128MB.
Implement 256MB and 512MB KSEG layouts:- add Kconfig selector for KSEG layout;
- add KSEG base address, size and alignment definitions to
arch/xtensa/include/asm/kmem_layout.h;
- use new definitions in TLB initialization;
- add build time memory map consistency checks.See Documentation/xtensa/mmu.txt for the details of new memory layouts.
Signed-off-by: Max Filippov
15 Jan, 2014
2 commits
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Use the simple-bus node to discover the io area, and remap the cached and
bypass io ranges. The parent-bus-address value of the first triplet in the
"ranges" property is used. This value is rounded down to the nearest 256MB
boundary. The length of the io area is fixed at 256MB; the "ranges" property
length value is ignored.Other limitations: (1) only the first simple-bus node is considered, and (2)
only the first triplet of the "ranges" property is considered.See ePAPR 1.1 §6.5 for the simple-bus node description, and §2.3.8 for the
"ranges" property description.Signed-off-by: Baruch Siach
Signed-off-by: Max Filippov -
Make the WT entry match table 4-52 of the Xtensa ISA RM (RD-2012.5).
Signed-off-by: Baruch Siach
Signed-off-by: Max Filippov
09 May, 2013
1 commit
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Signed-off-by: Max Filippov
Signed-off-by: Chris Zankel
19 Dec, 2012
1 commit
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In order to use S32C1I instruction on cores with ATOMCTL SR the register
must be properly initialized.Signed-off-by: Max Filippov
Signed-off-by: Chris Zankel