Eric Lee / smarc-fsl-linux-kernel

15 Apr, 2020

1 commit

09 Jan, 2020

1 commit

  • 8ae7d4423   spi: sh-msiof: Do not redefine STR while compile testing ... Browse Code »

    STR is a well-known stringify macro so it should be avoided in drivers
    to avoid warnings like this (MIPS architecture while compile testing):

    drivers/spi/spi-sh-msiof.c:76:0: warning: "STR" redefined
    #define STR 0x40 /* Status Register */
    arch/mips/include/asm/mipsregs.h:30:0: note: this is the location of the previous definition
    #define STR(x) __STR(x)

    To maintain consistency between all register names add a SI prefix to
    all of them. This also matches register names in datasheet.

    Signed-off-by: Krzysztof Kozlowski
    Reviewed-by: Geert Uytterhoeven
    Tested-by: Geert Uytterhoeven
    Link: https://lore.kernel.org/r/20200108194319.3171-1-krzk@kernel.org
    Signed-off-by: Mark Brown

    Krzysztof Kozlowski
     

08 Jan, 2020

1 commit

07 Aug, 2019

1 commit

02 Aug, 2019

1 commit

  • 6b8ac10e0   spi: Remove dev_err() usage after platform_get_irq() ... Browse Code »

    We don't need dev_err() messages when platform_get_irq() fails now that
    platform_get_irq() prints an error message itself when something goes
    wrong. Let's remove these prints with a simple semantic patch.

    //
    @@
    expression ret;
    struct platform_device *E;
    @@

    ret =
    (
    platform_get_irq(E, ...)
    |
    platform_get_irq_byname(E, ...)
    );

    if ( \( ret < 0 \| ret

    While we're here, remove braces on if statements that only have one
    statement (manually).

    Cc: Mark Brown
    Cc: linux-spi@vger.kernel.org
    Cc: Greg Kroah-Hartman
    Signed-off-by: Stephen Boyd
    Link: https://lore.kernel.org/r/20190730181557.90391-42-swboyd@chromium.org
    Signed-off-by: Mark Brown

    Stephen Boyd
     

28 May, 2019

1 commit

  • 635bdb7a3   spi: sh-msiof: Reduce delays in sh_msiof_modify_ctr_wait() ... Browse Code »

    While the Hardware User Manual does not document the maximum time needed
    for modifying bits in the MSIOF Control Register, experiments on R-Car
    Gen2/Gen3 and SH-Mobile AG5 revealed the following typical modification
    times for the various bits:
    - CTR.TXE and CTR.RXE: no delay,
    - CTR.TSCKE: less than 10 ns,
    - CTR.TFSE: up to a few hundred ns (depending on SPI transfer clock,
    i.e. less for faster transfers).
    There are no reasons to believe these figures are different for
    SH-MobileR2 SoCs (SH7723/SH7724).

    Hence the minimum busy-looping delay of 10 µs is excessive.
    Reduce the delay per loop iteration from 10 to 1 us, and the maximum
    delay from 1000 to 100 µs.

    Signed-off-by: Geert Uytterhoeven
    Signed-off-by: Mark Brown

    Geert Uytterhoeven
     

04 Apr, 2019

1 commit

  • 9fda66933   spi: sh-msiof: Convert to use GPIO descriptors ... Browse Code »

    Convert GPIO chip selects in the Renesas MSIOF SPI driver from legacy
    GPIO numbers to GPIO descriptors.

    Notes:
    - The board file for the SH7724-based Ecovec24 development board now
    registers a GPIO descriptor lookup, instead of passing a GPIO number
    through controller_data,
    - sh_msiof_get_cs_gpios() must release all GPIOs, else
    spi_get_gpio_descs() cannot claim them during SPI controller
    registration.

    Signed-off-by: Geert Uytterhoeven
    Signed-off-by: Mark Brown

    Geert Uytterhoeven
     

03 Apr, 2019

3 commits

04 Mar, 2019

1 commit

  • 0e836c3be   spi: sh-msiof: Restrict bits per word to 8/16/24/32 on R-Car Gen2/3 ... Browse Code »

    While the MSIOF variants in older SuperH and SH/R-Mobile SoCs support
    bits-per-word values in the full range 8..32, the variants present in
    R-Car Gen2 and Gen3 SoCs are restricted to 8, 16, 24, or 32.

    Obtain the value from family-specific sh_msiof_chipdata to fix this.

    Reported-by: Yoshihiro Shimoda
    Signed-off-by: Geert Uytterhoeven
    Reviewed-by: Simon Horman
    Signed-off-by: Mark Brown

    Geert Uytterhoeven
     

08 Feb, 2019

1 commit

19 Jan, 2019

2 commits

  • d05e3eadb   spi: sh-msiof: Use DMA if possible ... Browse Code »

    Currently, this driver only supports feature for DMA 32-bits.
    In this case, only if the data length is divisible by 4 to use
    DMA, otherwise PIO will be used. This patch will suggest use
    the DMA 32-bits with 4bytes of words, then the remaining data
    will be transmitted by PIO mode.

    Signed-off-by: Hoan Nguyen An
    Reviewed-by: Geert Uytterhoeven
    Tested-by: Geert Uytterhoeven
    Signed-off-by: Mark Brown

    Hoan Nguyen An
     
  • f70351ae0   spi: sh-msiof: fix *info pointer in request_dma() ... Browse Code »

    sh_msiof_spi_info *info struct pointer was initialized in the probe() function
    no need to get back and keep consistency.

    Signed-off-by: Hoan Nguyen An
    Reviewed-by: Geert Uytterhoeven
    Signed-off-by: Mark Brown

    Hoan Nguyen An
     

20 Dec, 2018

1 commit

05 Nov, 2018

1 commit

22 Oct, 2018

1 commit

15 Oct, 2018

1 commit

  • f34c6e625   spi: sh-msiof: fix deferred probing ... Browse Code »

    Since commit 9ec36cafe43b ("of/irq: do irq resolution in platform_get_irq")
    platform_get_irq() can return -EPROBE_DEFER. However, the driver overrides
    an error returned by that function with -ENOENT which breaks the deferred
    probing. Propagate upstream an error code returned by platform_get_irq()
    and remove the bogus "platform" from the error message, while at it...

    Fixes: 9ec36cafe43b ("of/irq: do irq resolution in platform_get_irq")
    Signed-off-by: Sergei Shtylyov
    Signed-off-by: Mark Brown

    Sergei Shtylyov
     

05 Sep, 2018

2 commits

  • 31a5fae4c   spi: sh-msiof: Fix handling of write value for SISTR register ... Browse Code »

    This patch changes writing to the SISTR register according to the H/W
    user's manual.

    The TDREQ bit and RDREQ bits of SISTR are read-only, and must be written
    their initial values of zero.

    Signed-off-by: Hiromitsu Yamasaki
    [geert: reword]
    Signed-off-by: Geert Uytterhoeven
    Signed-off-by: Mark Brown
    Cc: stable@vger.kernel.org

    Hiromitsu Yamasaki
     
  • ffa69d6a1   spi: sh-msiof: Fix invalid SPI use during system suspend ... Browse Code »

    If the SPI queue is running during system suspend, the system may lock
    up.

    Fix this by stopping/restarting the queue during system suspend/resume
    by calling spi_master_suspend()/spi_master_resume() from the PM
    callbacks. In-kernel users will receive an -ESHUTDOWN error while
    system suspend/resume is in progress.

    Signed-off-by: Gaku Inami
    Signed-off-by: Hiromitsu Yamasaki
    [geert: Cleanup, reword]
    Signed-off-by: Geert Uytterhoeven
    Signed-off-by: Mark Brown
    Cc: stable@vger.kernel.org

    Gaku Inami
     

29 Aug, 2018

1 commit

18 Jun, 2018

1 commit

  • 08ba7ae35   spi: sh-msiof: Make sure all DMA operations have completed ... Browse Code »

    In case of a bi-directional transfer, receive DMA may complete in the
    rcar-dmac driver before transmit DMA, due to scheduling latencies.
    As the MSIOF driver waits for completion of the receive DMA only, it may
    submit the next transmit DMA request before the previous one has
    completed.

    Make the driver more robust by waiting for the completion of both
    receive and transmit DMA, when applicable.

    Based on a patch in the BSP by Ryo Kataoka.

    Signed-off-by: Geert Uytterhoeven
    Signed-off-by: Mark Brown

    Geert Uytterhoeven
     

04 Jun, 2018

1 commit

24 May, 2018

1 commit

  • 0921e11e1   spi: sh-msiof: Fix setting SIRMDR1.SYNCAC to match SITMDR1.SYNCAC ... Browse Code »

    According to section 59.2.4 MSIOF Receive Mode Register 1 (SIRMDR1) in
    the R-Car Gen3 datasheet Rev.1.00, the value of the SIRMDR1.SYNCAC bit
    must match the value of the SITMDR1.SYNCAC bit. However,
    sh_msiof_spi_setup() changes only the latter.

    Fix this by updating the SIRMDR1 register like the SITMDR1 register,
    taking into account register bits that exist in SITMDR1 only.

    Reported-by: Renesas BSP team via Yoshihiro Shimoda
    Fixes: 7ff0b53c4051145d ("spi: sh-msiof: Avoid writing to registers from spi_master.setup()")
    Signed-off-by: Geert Uytterhoeven
    Reviewed-by: Simon Horman
    Signed-off-by: Mark Brown

    Geert Uytterhoeven
     

17 Apr, 2018

1 commit

  • 51093cba2   spi: sh-msiof: Simplify calculation of divisors for transfer rate ... Browse Code »

    The change updates sh_msiof_spi_set_clk_regs() function by iterating
    over BRDV power values. Note that the change is a functional one, namely
    prescaler output x 1/1 set in BRDV bit field (0b111) for MSO division
    rate set to 2 is substituted by BRDV = 0b000 and BRPS = 0b0, in terms
    of written values to TSCR setting of 0x0107 is substituted by 0x0000,
    and for all input parameter cases this is the only functional change,
    which touches the controller.

    As a result of the rework the function is supposed to be slightly more
    efficient and more readable and maintainable in case of any further
    extensions.

    Signed-off-by: Vladimir Zapolskiy
    Signed-off-by: Mark Brown

    Vladimir Zapolskiy
     

16 Apr, 2018

1 commit

  • 10b464083   spi: sh-msiof: Fix bit field overflow writes to TSCR/RSCR ... Browse Code »

    The change fixes a bit field overflow which allows to write to higher
    bits while calculating SPI transfer clock and setting BRPS and BRDV
    bit fields, the problem is reproduced if 'parent_rate' to 'spi_hz'
    ratio is greater than 1024, for instance

    p->min_div = 2,
    MSO rate = 33333333,
    SPI device rate = 10000

    results in

    k = 5, i.e. BRDV = 0b100 or 1/32 prescaler output,
    BRPS = 105,
    TSCR value = 0x6804, thus MSSEL and MSIMM bit fields are non-zero.

    Fixes: 65d5665bb260 ("spi: sh-msiof: Update calculation of frequency dividing")
    Signed-off-by: Vladimir Zapolskiy
    Signed-off-by: Mark Brown

    Vladimir Zapolskiy
     

22 Mar, 2018

1 commit

  • da779513d   spi: sh-msiof: Use correct enum for DMA transfer direction ... Browse Code »

    Use enum dma_transfer_direction as required by dmaengine_prep_slave_sg()
    instead of enum dma_data_direction. This won't change behavior in
    practice as the enum values are equivalent.

    This fixes two warnings when building with clang:
    drivers/spi/spi-sh-msiof.c:755:27: warning: implicit conversion from enumeration
    type 'enum dma_data_direction' to different enumeration type
    'enum dma_transfer_direction' [-Wenum-conversion]
    rx->sgl, rx->nents, DMA_FROM_DEVICE,
    ^~~~~~~~~~~~~~~
    drivers/spi/spi-sh-msiof.c:772:27: warning: implicit conversion from enumeration
    type 'enum dma_data_direction' to different enumeration type
    'enum dma_transfer_direction' [-Wenum-conversion]
    tx->sgl, tx->nents, DMA_TO_DEVICE,
    ^~~~~~~~~~~~~

    Based on commit 768d59f5d0139a6f ("spi: rspi: use correct enum for DMA
    transfer direction").

    Signed-off-by: Geert Uytterhoeven
    Reviewed-by: Stefan Agner
    Signed-off-by: Mark Brown

    Geert Uytterhoeven
     

27 Jan, 2018

1 commit

04 Jan, 2018

1 commit

  • 89434c3c3   spi: sh-msiof: Fix timeout failures for TX-only DMA transfers ... Browse Code »

    When using RX (with or without TX), the DMA interrupt triggers
    completion when the RX FIFO has been emptied, i.e. after the full
    transfer has finished.

    However, when using TX without RX, the DMA interrupt triggers completion
    as soon as the DMA engine has filled the TX FIFO, i.e. before the full
    transfer has finished. Then sh_msiof_modify_ctr_wait() will spin until
    the transfer has really finished and the TFSE bit is cleared, for at
    most 1 ms. For slow speeds and/or large transfers, this may cause
    timeouts and transfer failures:

    spi_sh_msiof e6e10000.spi: failed to shut down hardware
    74x164 spi2.0: SPI transfer failed: -110
    spi_master spi2: failed to transfer one message from queue
    74x164 spi2.0: Failed writing: -110

    Fix this by waiting explicitly until the TX FIFO has been emptied.

    Based on a patch in the BSP by Hiromitsu Yamasaki.

    Signed-off-by: Geert Uytterhoeven
    Signed-off-by: Mark Brown

    Geert Uytterhoeven
     

14 Dec, 2017

3 commits

  • b8761434b   spi: sh-msiof: Implement cs-gpios configuration ... Browse Code »

    The current support for GPIO chip selects assumes the GPIOs have been
    configured by platform code or the boot loader. This includes pinmux
    setup and GPIO direction. Hence it does not work as expected when just
    described in DT using the "cs-gpios" property.

    Fix this by:
    1. using devm_gpiod_get_index() to request the GPIO, and thus
    configure pinmux, if needed,
    2. configuring the GPIO direction is the spi_master.setup() callback.

    Use gpio_is_valid() instead of a check on positive numbers.

    Note that when using GPIO chip selects, at least one native chip select
    must be left unused, as that native chip select will be driven anyway,
    and (global) native chip select polarity must be taken into account.

    Signed-off-by: Geert Uytterhoeven
    Signed-off-by: Mark Brown

    Geert Uytterhoeven
     
  • 9cce882be   spi: sh-msiof: Extend support to 3 native chip selects ... Browse Code »

    Currently only the MSIOF_SYNC signal can be used as a native chip
    select. Extend support to up to 3 native chipselects using the
    MSIOF_SS1 and MSIOF_SS2 signals.

    Inspired by a patch in the BSP by Hiromitsu Yamasaki.

    Signed-off-by: Geert Uytterhoeven
    Signed-off-by: Mark Brown

    Geert Uytterhoeven
     
  • 7ff0b53c4   spi: sh-msiof: Avoid writing to registers from spi_master.setup() ... Browse Code »

    The spi_master.setup() callback must not change configuration registers,
    as that could corrupt I/O that is in progress for other SPI slaves.

    The only exception is the configuration of the native chip select
    polarity in SPI master mode, as a wrong chip select polarity will cause
    havoc during all future transfers to any other SPI slave.

    Hence stop writing to registers in sh_msiof_spi_setup(), unless it is
    the first call for a controller using a native chip select, or unless
    native chip select polarity has changed (note that you'll loose anyway
    if I/O is in progress). Even then, only do what is strictly necessary,
    instead of calling sh_msiof_spi_set_pin_regs().

    Signed-off-by: Geert Uytterhoeven
    Signed-off-by: Mark Brown

    Geert Uytterhoeven
     

01 Dec, 2017

1 commit

11 Nov, 2017

1 commit

04 Nov, 2017

1 commit

02 Nov, 2017

1 commit

04 Oct, 2017

1 commit

26 Sep, 2017

1 commit

17 Jul, 2017

1 commit

26 May, 2017

1 commit

  • cf9e4784f   spi: sh-msiof: Add slave mode support ... Browse Code »

    Add slave mode support to the MSIOF driver, in both PIO and DMA mode.

    For now this only supports the transmission of messages with a size
    that is known in advance.

    Signed-off-by: Hisashi Nakamura
    Signed-off-by: Hiromitsu Yamasaki
    [geert: Timeout handling cleanup, spi core integration, cancellation,
    rewording]
    Signed-off-by: Geert Uytterhoeven
    Acked-by: Rob Herring
    Signed-off-by: Mark Brown

    Hisashi Nakamura