08 Jun, 2017
40 commits
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Add i.MX7ULP MSL support.
Signed-off-by: Anson Huang
Signed-off-by: Fugang Duan -
Add i.MX7ULP clock driver.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
Signed-off-by: Fancy Fang -
Add below new clock types to support new SoC:
composite clk;
frac-divider;
pfdv2;
pllv4.These clock types are for i.MX7ULP and maybe
following SoCs.Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
[Octavian: fix build warning by using u64 in do_div ops]
Signed-off-by: Octavian Purdila -
Add i.MX TPM support for clock source.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping -
Add i.MX7ULP EVK board support.
Signed-off-by: Anson Huang
Signed-off-by: Shenwei Wang
Signed-off-by: Fancy Fang
Signed-off-by: ye li -
Add i.MX7ULP dtsi support.
Signed-off-by: Anson Huang
Signed-off-by: Shenwei Wang
Signed-off-by: Fugang Duan
Signed-off-by: Bai Ping
Signed-off-by: Gan Yuchou
Signed-off-by: Ye.Li
Signed-off-by: Haibo Chen
Signed-off-by: Han Xu
Signed-off-by: Richard Zhu
Signed-off-by: Peter Chen
Signed-off-by: Robin Gong
Signed-off-by: Gao Pan
Signed-off-by: Fancy Fang
Signed-off-by: Xianzhong -
Add imx7ulp header file.
Two changes base on original header file from iomux tool team:
- Remove the mux register column since mux and conf is shared in
one register.
- IOMUX_0 part:
The register address: 0x4103_d000 ~ 0x4103_d0cc, the header file
offset is 0xdxxx, now change it to 0x0xxx. The common base address
0x4103_d000 is defined by dts file.Signed-off-by: Fugang Duan
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PWM driver expects two clocks, so correct it to meet this requirement.
Otherwise pwm can not work properly, neither does the backlight (using pwm1).Signed-off-by: Robby Cai
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When usdhc driver remove, also need to release bus frequency.
Signed-off-by: Haibo Chen
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Add support for the epop i.MX6SX SCM EVB board
The epop variant contains an eMMC(512MB) within the
POP package.Support the next features for epop 6sxscm EVB:
- Regular epop board
- M4 supportSigned-off-by: Alejandro Sierra
Signed-off-by: Juan Gutierrez -
Add the generic dtsi configuration to support EMMC on the
i.MX6SX SCM platformsSigned-off-by: Alejandro Sierra
Signed-off-by: Juan Gutierrez -
Add the generic dtsi configuration support for the i.MX6SX SCM
platforms with 512MB of DDR memory mapping.Signed-off-by: Juan Gutierrez
Signed-off-by: Alejandro Sierra -
Add support for the 1gb i.MX6SX SCM EVB board
Support the next features for 1Gb 6sxscm EVB:
- Regular 1gb board
- M4 support
- MQS
- SAI sound card
- LCD and HDMI with sii902x support
- Bluetooth and Wifi Murata ZP SDIO dongleSigned-off-by: Alejandro Sierra
Signed-off-by: Juan Gutierrez -
Add the generic dts configuration support, including BT and
Wifi for the i.MX6SX SCM Evaluation Board (EVB)- Generic DTS for 6SXSCM EVB
- Bluetooth and Wifi
- LDO enabledSigned-off-by: Juan Gutierrez
Signed-off-by: Alejandro Sierra -
The initial version is wrong, fix it.
Signed-off-by: Robin Gong
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Add Micrel phy initialization for imx6sxscm evb platform
Signed-off-by: Alejandro Sierra
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When a device like (USB, CAMM, tty, etc) prevents the megamix
domain to power down during the suspend process (by enabling
a wakeup source) the resume process goes through a path where
the MMDC context should not be restored. However this resume
path does not reset the read fifo MMDCx_MPDGCTRL0[RST_RD_FIFO]
for the platforms with LPDDR2 causing a bad resuming and reset
of the device due to an exception.This patch adds the reset_read_fifo on the No-restoring-MMDC
path to fix the bad resuming.Signed-off-by: Juan Gutierrez
Signed-off-by: Alejandro Sierra -
vring memory address was hardcoded at the top of the 1GB RAM.
For systems with a memory map with less or different than 1GB,
the hardcoded value might be not correct and cause issues.This patch add the support to pass the vring address from device
tree configuration on the reg platform argument in the following
format:reg =
For example, for a 512MB system, with the rpmgs vring placed at
top of the memory the configuration will look like below:&rpmsg{
reg = ;
};Signed-off-by: Juan Gutierrez
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Add Murata Type ZP (BCM4339) module support on i.MX6SLL platforms:
- i.MX6SLL EVK (SD3 slot + BT connector) + Murata adapter V2.0Signed-off-by: Fugang Duan
Signed-off-by: Dong Aisheng -
This reverts commit 3d7dd5ec903bc867c0274ac871b707839712f832.
This commit is wrongly pushed and also it breaks build, revert it.
Signed-off-by: Jason Liu
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Add support for SCM i.MX6DQ 1Gb Evaluation Board (EVB).
Support the next features for 1Gb EVB boards:
- Support for fix and interleave mode
- For fix mode additional dts are provided for:
- hdcp
- enetirq
- bluetooth and wifi for Murata ZP SDIO dongleSigned-off-by: Alejandro Sierra
Signed-off-by: Juan Gutierrez -
Add support for SCM i.MX6DQ 1Gb Quick Start Board (QWKS).
Support the next features for 1Gb QWKS boards:
- Support for fix and interleave mode
- For fix mode additional dts are provided for
- hdcp
- Wifi with Murata ZP SDIO dongleSigned-off-by: Juan Gutierrez
Signed-off-by: Alejandro Sierra -
Add the generic dtsi configuration support for the SCM i.MX6DQ
QWKS and EVB board with 1GB of DDR memory mappingSigned-off-by: Juan Gutierrez
Signed-off-by: Alejandro Sierra -
Add the generic dtsi configuration support, including
Wifi, for the SCM i.MX6DQ Quick Start Board (QWKS)Signed-off-by: Juan Gutierrez
Signed-off-by: Alejandro Sierra -
Add the support for a CT36X based touchscreens using
the CT36X controller and i2c touchscreen interface.Signed-off-by: Alejandro Lozano
Signed-off-by: Juan Gutierrez
Signed-off-by: Alejandro Sierra -
MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64
and LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high
performance, and optimized. MMDC is present on i.MX6 Quad and i.MX6
QuadPlus devices, but this driver only supports i.MX6 Quad at the moment.
MMDC provides registers for performance counters which read via this
driver to help debug memory throughput and similar issues.$ perf stat -a -e mmdc/busy-cycles/,mmdc/read-accesses/,mmdc/read-bytes/,mmdc/total-cycles/,mmdc/write-accesses/,mmdc/write-bytes/ dd if=/dev/zero of=/dev/null bs=1M count=5000
Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=1M count=5000':898021787 mmdc/busy-cycles/
14819600 mmdc/read-accesses/
471.30 MB mmdc/read-bytes/
2815419216 mmdc/total-cycles/
13367354 mmdc/write-accesses/
427.76 MB mmdc/write-bytes/5.334757334 seconds time elapsed
Signed-off-by: Zhengyu Shen
Signed-off-by: Frank Li
Signed-off-by: Shawn Guo -
Add i.MX6SLL support in imx_v7_mfg_defconfig.
Signed-off-by: Bai Ping
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When suspend usdhc, it will access usdhc register. So usdhc clock
should be enabled, otherwise the access usdhc register will return
error or cause system.Take this into consideration, if system enable a usdhc and do not
connect any SD/SDIO/MMC card, after system boot up, this usdhc
will do runtime suspend, and close all usdhc clock. At this time,
if suspend the system, due to no card persent, usdhc runtime resume
will not be called. So usdhc clock still closed, then in suspend,
once access usdhc register, system hung or bus error return.This patch make sure usdhc clock always enabled while doing usdhc
suspend.Signed-off-by: Haibo Chen
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1.8v of imx7d pcie phy, should be turned on after
the 1p0d(1.0v) of pcie phy is turned on.
And turned off before the 1p0d(1.0v) of pcie phy
is turned offSigned-off-by: Richard Zhu
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Add one new regulator events macro 'REGULATOR_EVENT_AFT_DO_ENABLE'.
1.8v of imx7d pcie phy, should be turned on after
the 1p0d(1.0v) of pcie phy is turned on.Signed-off-by: Richard Zhu
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Add the AFT_ENABLE event macros, because that
1.8v of imx7d pcie phy, should be turned on after
the 1p0d(1.0v) of pcie phy is turned on.Signed-off-by: Richard Zhu
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Do not set the override bit of 1p0d regulator.
Because, the 1p0d and the vdd1.8v should be turned on
separately by the requirements of the imx7d pcie phy.Signed-off-by: Richard Zhu
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The ep rc validation is failed on imx6dl.
Root cause:
The ref clk of imx6dl pcie is 100M(bit20 of PLL_ENET).
But the driver doesn't enable it.
Solution:
enable pci_bus clock in ep rc validation system, since
the parent of the pci_bus is the 100M.
The connection between ep and rc only have the TX/RX
parirs, there is no impaction when enable the pcie_bus
in pcie ep rc validation system.Signed-off-by: Richard Zhu
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Add PXP V4L2 output support
Signed-off-by: Robby Cai
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Enable USBOTG1
Signed-off-by: Peter Chen
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As on i.MX6SLL, there is no ARM LDO, the code for ARM LDO
bypass check is unnecessary, remove these piece of code in
i.MX6SLL low power idle.Signed-off-by: Bai Ping
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This reverts commit 2c01452f4d7c0f65553b365adc27a1b7b6ba8644.
Besides, add other SoC request high bus freq. This is because
only imx6qdl do not implement low bus idle, so imx6qdl can work
well under low power mode without request high bus freq which
also can save power. For other SoC, need to request high bus
freq when usdhc is active.Also can refer to commit 312979d1fcbd.
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The timing settings for 100MHz are almost the same as the ones for
400MHz except for the MMDCx_MISC[RALAT] parameter which needs to be
set to 2 cycles.For the 100MHz case the restoration of the mmdc setting should be performed
in 2 steps: restore the mmdc setting and then overwrite the RALAT setting
for 2 cycles.A decision code within the "mmdc_clk_lower_equal_100MHz" macro is added
to go to the "equal to 100MHz" or to the "lower to 100MHz" caseSigned-off-by: Juan Gutierrez
Signed-off-by: Alejandro Lozano -
Setting the Read Additional Latency (RALAT) to 2 cycles,
MMDCx_MDMISC[RALAT] = 2, is needed for 24MHz operation point.Currently this is set within the "set_timings_below_100MHz_operation"
macro, which is use for the 24MHz case.In order to provide a generic way for setting RALAT=2 the code
is wrapped in this new macro: "set_mmdc_misc_ralat_2_cycles", so
other set points (besides the below 100MHz case) can reuse this code.As an example, for 100Mhz operation the RALAT should be set to 2 cycles,
however, the rest of the MMDCFG parameter are not the same as in the
"below_100MHz" case. So, this macro can be reused for its RALAT part.Signed-off-by: Juan Gutierrez
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Two macros are renamed:
1) set_timings_above_100MHz_operation as restore_mmdc_settings_info
2) mmdc_clk_lower_100MHz as mmdc_clk_lower_equal_100MHzFor (1) the operation is generic to several cases and not just related
(at least on a semantic way) with the operations "above" 100MHzRenamed as restore_mmdc_settings_info the macro can be reused for the
other cases like equal to 100MHz and possibly other intermediate
operation points.For (2), the macro is renamed as mmdc_clk_lower_equal_100MHz to reflect
that this macro handles both the "lower than 100 MHz" case and the
"equal to 100MHz" case.Signed-off-by: Juan Gutierrez