Eric Lee / smarc-fsl-linux-kernel

18 Apr, 2019

5 commits

24 Mar, 2019

4 commits

  • e19ca3fe6   clocksource/drivers/arch_timer: Workaround for Allwinner A64 timer instability ... Browse Code »

    commit c950ca8c35eeb32224a63adc47e12f9e226da241 upstream.

    The Allwinner A64 SoC is known[1] to have an unstable architectural
    timer, which manifests itself most obviously in the time jumping forward
    a multiple of 95 years[2][3]. This coincides with 2^56 cycles at a
    timer frequency of 24 MHz, implying that the time went slightly backward
    (and this was interpreted by the kernel as it jumping forward and
    wrapping around past the epoch).

    Investigation revealed instability in the low bits of CNTVCT at the
    point a high bit rolls over. This leads to power-of-two cycle forward
    and backward jumps. (Testing shows that forward jumps are about twice as
    likely as backward jumps.) Since the counter value returns to normal
    after an indeterminate read, each "jump" really consists of both a
    forward and backward jump from the software perspective.

    Unless the kernel is trapping CNTVCT reads, a userspace program is able
    to read the register in a loop faster than it changes. A test program
    running on all 4 CPU cores that reported jumps larger than 100 ms was
    run for 13.6 hours and reported the following:

    Count | Event
    -------+---------------------------
    9940 | jumped backward 699ms
    268 | jumped backward 1398ms
    1 | jumped backward 2097ms
    16020 | jumped forward 175ms
    6443 | jumped forward 699ms
    2976 | jumped forward 1398ms
    9 | jumped forward 356516ms
    9 | jumped forward 357215ms
    4 | jumped forward 714430ms
    1 | jumped forward 3578440ms

    This works out to a jump larger than 100 ms about every 5.5 seconds on
    each CPU core.

    The largest jump (almost an hour!) was the following sequence of reads:
    0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000

    Note that the middle bits don't necessarily all read as all zeroes or
    all ones during the anomalous behavior; however the low 10 bits checked
    by the function in this patch have never been observed with any other
    value.

    Also note that smaller jumps are much more common, with backward jumps
    of 2048 (2^11) cycles observed over 400 times per second on each core.
    (Of course, this is partially explained by lower bits rolling over more
    frequently.) Any one of these could have caused the 95 year time skip.

    Similar anomalies were observed while reading CNTPCT (after patching the
    kernel to allow reads from userspace). However, the CNTPCT jumps are
    much less frequent, and only small jumps were observed. The same program
    as before (except now reading CNTPCT) observed after 72 hours:

    Count | Event
    -------+---------------------------
    17 | jumped backward 699ms
    52 | jumped forward 175ms
    2831 | jumped forward 699ms
    5 | jumped forward 1398ms

    Further investigation showed that the instability in CNTPCT/CNTVCT also
    affected the respective timer's TVAL register. The following values were
    observed immediately after writing CNVT_TVAL to 0x10000000:

    CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error
    --------------------+------------+--------------------+-----------------
    0x000000d4a2d8bfff | 0x10003fff | 0x000000d4b2d8bfff | +0x00004000
    0x000000d4a2d94000 | 0x0fffffff | 0x000000d4b2d97fff | -0x00004000
    0x000000d4a2d97fff | 0x10003fff | 0x000000d4b2d97fff | +0x00004000
    0x000000d4a2d9c000 | 0x0fffffff | 0x000000d4b2d9ffff | -0x00004000

    The pattern of errors in CNTV_TVAL seemed to depend on exactly which
    value was written to it. For example, after writing 0x10101010:

    CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error
    --------------------+------------+--------------------+-----------------
    0x000001ac3effffff | 0x1110100f | 0x000001ac4f10100f | +0x1000000
    0x000001ac40000000 | 0x1010100f | 0x000001ac5110100f | -0x1000000
    0x000001ac58ffffff | 0x1110100f | 0x000001ac6910100f | +0x1000000
    0x000001ac66000000 | 0x1010100f | 0x000001ac7710100f | -0x1000000
    0x000001ac6affffff | 0x1110100f | 0x000001ac7b10100f | +0x1000000
    0x000001ac6e000000 | 0x1010100f | 0x000001ac7f10100f | -0x1000000

    I was also twice able to reproduce the issue covered by Allwinner's
    workaround[4], that writing to TVAL sometimes fails, and both CVAL and
    TVAL are left with entirely bogus values. One was the following values:

    CNTVCT | CNTV_TVAL | CNTV_CVAL
    --------------------+------------+--------------------------------------
    0x000000d4a2d6014c | 0x8fbd5721 | 0x000000d132935fff (615s in the past)
    Reviewed-by: Marc Zyngier

    ========================================================================

    Because the CPU can read the CNTPCT/CNTVCT registers faster than they
    change, performing two reads of the register and comparing the high bits
    (like other workarounds) is not a workable solution. And because the
    timer can jump both forward and backward, no pair of reads can
    distinguish a good value from a bad one. The only way to guarantee a
    good value from consecutive reads would be to read _three_ times, and
    take the middle value only if the three values are 1) each unique and
    2) increasing. This takes at minimum 3 counter cycles (125 ns), or more
    if an anomaly is detected.

    However, since there is a distinct pattern to the bad values, we can
    optimize the common case (1022/1024 of the time) to a single read by
    simply ignoring values that match the error pattern. This still takes no
    more than 3 cycles in the worst case, and requires much less code. As an
    additional safety check, we still limit the loop iteration to the number
    of max-frequency (1.2 GHz) CPU cycles in three 24 MHz counter periods.

    For the TVAL registers, the simple solution is to not use them. Instead,
    read or write the CVAL and calculate the TVAL value in software.

    Although the manufacturer is aware of at least part of the erratum[4],
    there is no official name for it. For now, use the kernel-internal name
    "UNKNOWN1".

    [1]: https://github.com/armbian/build/commit/a08cd6fe7ae9
    [2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/
    [3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26
    [4]: https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clocksource/arm_arch_timer.c#L272

    Acked-by: Maxime Ripard
    Tested-by: Andre Przywara
    Signed-off-by: Samuel Holland
    Cc: stable@vger.kernel.org
    Signed-off-by: Daniel Lezcano
    Signed-off-by: Greg Kroah-Hartman

    Samuel Holland
     
  • ef8062e20   clocksource/drivers/exynos_mct: Clear timer interrupt when shutdown ... Browse Code »

    commit d2f276c8d3c224d5b493c42b6cf006ae4e64fb1c upstream.

    When shutting down the timer, ensure that after we have stopped the
    timer any pending interrupts are cleared. This fixes a problem when
    suspending, as interrupts are disabled before the timer is stopped,
    so the timer interrupt may still be asserted, preventing the system
    entering a low power state when the wfi is executed.

    Signed-off-by: Stuart Menefy
    Reviewed-by: Krzysztof Kozlowski
    Tested-by: Marek Szyprowski
    Cc: # v4.3+
    Signed-off-by: Daniel Lezcano
    Signed-off-by: Greg Kroah-Hartman

    Stuart Menefy
     
  • c1f45c10d   clocksource/drivers/exynos_mct: Move one-shot check from tick clear to ISR ... Browse Code »

    commit a5719a40aef956ba704f2aa1c7b977224d60fa96 upstream.

    When a timer tick occurs and the clock is in one-shot mode, the timer
    needs to be stopped to prevent it triggering subsequent interrupts.
    Currently this code is in exynos4_mct_tick_clear(), but as it is
    only needed when an ISR occurs move it into exynos4_mct_tick_isr(),
    leaving exynos4_mct_tick_clear() just doing what its name suggests it
    should.

    Signed-off-by: Stuart Menefy
    Reviewed-by: Krzysztof Kozlowski
    Tested-by: Marek Szyprowski
    Cc: stable@vger.kernel.org # v4.3+
    Signed-off-by: Daniel Lezcano
    Signed-off-by: Greg Kroah-Hartman

    Stuart Menefy
     
  • ac696b017   clocksource: timer-ti-dm: Fix pwm dmtimer usage of fck reparenting ... Browse Code »

    [ Upstream commit 983a5a43ec254cd5ddf3254db80ca96e8f8bb2a4 ]

    Commit 84badc5ec5fc ("ARM: dts: omap4: Move l4 child devices to probe
    them with ti-sysc") moved some omap4 timers to probe with ti-sysc
    interconnect target module. Turns out this broke pwm-omap-dmtimer
    where we now try to reparent the clock to itself with the following:

    omap_dm_timer_of_set_source: failed to set parent

    With ti-sysc, we can now configure the clock sources in the dts
    with assigned-clocks and assigned-clock-parents. So we should be able
    to remove omap_dm_timer_of_set_source with clean-up patches later on.
    But for now, let's just fix it first by checking if parent and fck
    are the same and bail out of so.

    Fixes: 84badc5ec5fc ("ARM: dts: omap4: Move l4 child devices to probe them with ti-sysc")
    Cc: Bartosz Golaszewski
    Cc: Daniel Lezcano
    Cc: H. Nikolaus Schaller
    Cc: Keerthy
    Cc: Ladislav Michl
    Cc: Pavel Machek
    Cc: Sebastian Reichel
    Cc: Tero Kristo
    Cc: Thierry Reding
    Cc: Thomas Gleixner
    Reported-by: H. Nikolaus Schaller
    Tested-By: Andreas Kemnade
    Tested-By: H. Nikolaus Schaller
    Signed-off-by: Tony Lindgren
    Signed-off-by: Sasha Levin

    Tony Lindgren
     

26 Jan, 2019

1 commit

  • decca9bc2   clocksource/drivers/integrator-ap: Add missing of_node_put() ... Browse Code »

    [ Upstream commit 5eb73c831171115d3b4347e1e7124a5a35d8086c ]

    The function of_find_node_by_path() acquires a reference to the node
    returned by it and that reference needs to be dropped by its caller.

    integrator_ap_timer_init_of() doesn't do that. The pri_node and the
    sec_node are used as an identifier to compare against the current
    node, so we can directly drop the refcount after getting the node from
    the path as it is not used as pointer.

    By dropping the refcount right after getting it, a single variable is
    needed instead of two.

    Fix this by use a single variable and drop the refcount right after
    of_find_node_by_path().

    Signed-off-by: Yangtao Li
    Signed-off-by: Daniel Lezcano
    Signed-off-by: Sasha Levin

    Yangtao Li
     

10 Jan, 2019

1 commit

  • bf75d9382   clocksource/drivers/arc_timer: Utilize generic sched_clock ... Browse Code »

    commit bf287607c80f24387fedb431a346dc67f25be12c upstream.

    It turned out we used to use default implementation of sched_clock()
    from kernel/sched/clock.c which was as precise as 1/HZ, i.e.
    by default we had 10 msec granularity of time measurement.

    Now given ARC built-in timers are clocked with the same frequency as
    CPU cores we may get much higher precision of time tracking.

    Thus we switch to generic sched_clock which really reads ARC hardware
    counters.

    This is especially helpful for measuring short events.
    That's what we used to have:
    ------------------------------>8------------------------
    $ perf stat /bin/sh -c /root/lmbench-master/bin/arc/hello > /dev/null

    Performance counter stats for '/bin/sh -c /root/lmbench-master/bin/arc/hello':

    10.000000 task-clock (msec) # 2.832 CPUs utilized
    1 context-switches # 0.100 K/sec
    1 cpu-migrations # 0.100 K/sec
    63 page-faults # 0.006 M/sec
    3049480 cycles # 0.305 GHz
    1091259 instructions # 0.36 insn per cycle
    256828 branches # 25.683 M/sec
    27026 branch-misses # 10.52% of all branches

    0.003530687 seconds time elapsed

    0.000000000 seconds user
    0.010000000 seconds sys
    ------------------------------>8------------------------

    And now we'll see:
    ------------------------------>8------------------------
    $ perf stat /bin/sh -c /root/lmbench-master/bin/arc/hello > /dev/null

    Performance counter stats for '/bin/sh -c /root/lmbench-master/bin/arc/hello':

    3.004322 task-clock (msec) # 0.865 CPUs utilized
    1 context-switches # 0.333 K/sec
    1 cpu-migrations # 0.333 K/sec
    63 page-faults # 0.021 M/sec
    2986734 cycles # 0.994 GHz
    1087466 instructions # 0.36 insn per cycle
    255209 branches # 84.947 M/sec
    26002 branch-misses # 10.19% of all branches

    0.003474829 seconds time elapsed

    0.003519000 seconds user
    0.000000000 seconds sys
    ------------------------------>8------------------------

    Note how much more meaningful is the second output - time spent for
    execution pretty much matches number of cycles spent (we're runnign
    @ 1GHz here).

    Signed-off-by: Alexey Brodkin
    Cc: Daniel Lezcano
    Cc: Vineet Gupta
    Cc: Thomas Gleixner
    Cc: stable@vger.kernel.org
    Acked-by: Vineet Gupta
    Signed-off-by: Daniel Lezcano
    Signed-off-by: Greg Kroah-Hartman

    Alexey Brodkin
     

21 Nov, 2018

1 commit

  • ebbc6fce6   clockevents/drivers/i8253: Add support for PIT shutdown quirk ... Browse Code »

    commit 35b69a420bfb56b7b74cb635ea903db05e357bec upstream.

    Add support for platforms where pit_shutdown() doesn't work because of a
    quirk in the PIT emulation. On these platforms setting the counter register
    to zero causes the PIT to start running again, negating the shutdown.

    Provide a global variable that controls whether the counter register is
    zero'ed, which platform specific code can override.

    Signed-off-by: Michael Kelley
    Signed-off-by: Thomas Gleixner
    Cc: "gregkh@linuxfoundation.org"
    Cc: "devel@linuxdriverproject.org"
    Cc: "daniel.lezcano@linaro.org"
    Cc: "virtualization@lists.linux-foundation.org"
    Cc: "jgross@suse.com"
    Cc: "akataria@vmware.com"
    Cc: "olaf@aepfle.de"
    Cc: "apw@canonical.com"
    Cc: vkuznets
    Cc: "jasowang@redhat.com"
    Cc: "marcelo.cerri@canonical.com"
    Cc: KY Srinivasan
    Cc: stable@vger.kernel.org
    Link: https://lkml.kernel.org/r/1541303219-11142-2-git-send-email-mikelley@microsoft.com
    Signed-off-by: Greg Kroah-Hartman

    Michael Kelley
     

27 Sep, 2018

1 commit

24 Sep, 2018

1 commit

  • 4451d3f59   clocksource/drivers/fttmr010: Fix set_next_event handler ... Browse Code »

    Currently, the aspeed MATCH1 register is updated to in set_next_event handler, with the assumption that COUNT
    register value is preserved when the timer is disabled and it continues
    decrementing after the timer is enabled. But the assumption is wrong:
    RELOAD register is loaded into COUNT register when the aspeed timer is
    enabled, which means the next event may be delayed because timer
    interrupt won't be generated until .

    The problem can be fixed by updating RELOAD register to , and
    COUNT register will be re-loaded when the timer is enabled and interrupt
    is generated when COUNT register overflows.

    The test result on Facebook Backpack-CMM BMC hardware (AST2500) shows
    the issue is fixed: without the patch, usleep(100) suspends the process
    for several milliseconds (and sometimes even over 40 milliseconds);
    after applying the fix, usleep(100) takes averagely 240 microseconds to
    return under the same workload level.

    Signed-off-by: Tao Ren
    Reviewed-by: Linus Walleij
    Tested-by: Lei YU
    Signed-off-by: Daniel Lezcano

    Tao Ren
     

13 Sep, 2018

1 commit

20 Aug, 2018

1 commit

  • 1009aa120   Merge tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kerne… ... Browse Code »

    …l/git/palmer/riscv-linux

    Pull RISC-V updates from Palmer Dabbelt:
    "This contains some major improvements to the RISC-V port, including
    the necessary interrupt controller and timer support to actually make
    it to userspace. Support for three devices has been added:

    - the ISA-mandated timers on RISC-V systems.

    - the ISA-mandated first-level interrupt controller on RISC-V
    systems, which is handled as part of our core arch code because
    it's very small and tightly tied to the ISA.

    - SiFive's platform-level interrupt controller, which talks to the
    actual devices.

    In addition to these new devices, there are a handful of cleanups all
    over the RISC-V tree:

    - build fixes for various configurations:
    * A fix to the vDSO build's makefile so it respects CFLAGS.
    * The addition of __lshrti3, a libgcc derived function necessary
    for some 32-bit configurations.
    * !SMP && PERF_EVENTS

    - Cleanups to the arch code to remove the remnants of old versions of
    the drivers that were just properly submitted.
    * Some dead code from the timer driver, most of which wasn't ever
    even compiled.
    * Cleanups of some interrupt #defines, which are now local to the
    interrupt handling code.

    - Fixes to ptrace(), which while not being sufficient to fully make
    GDB work are at least sufficient to get simple GDB tasks to work.

    - Early printk support via RISC-V's architecturally mandated SBI
    console device.

    - A fix to our early debug trap handler to ensure it's always
    aligned.

    These patches have all been through a fairly extensive review process,
    but as this enables a whole pile of functionality (ie, userspace) I'm
    confident we'll need to submit a few more patches. The only concrete
    issues I know about are the sys_riscv_flush_icache patches, but as I
    managed to screw those up on Friday I figured it'd be best to let them
    bake another week.

    This tag boots a Fedora root filesystem on QEMU's master branch for
    me, and before this morning's rebase (from 4.18-rc8 to 4.18) it booted
    on the HiFive Unleashed.

    Thanks to Christoph Hellwig and the other guys at WD for getting the
    new drivers in shape!"

    * tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
    dt-bindings: interrupt-controller: SiFive Plaform Level Interrupt Controller
    dt-bindings: interrupt-controller: RISC-V local interrupt controller
    RISC-V: Fix !CONFIG_SMP compilation error
    irqchip: add a SiFive PLIC driver
    RISC-V: Add the directive for alignment of stvec's value
    clocksource: new RISC-V SBI timer driver
    RISC-V: implement low-level interrupt handling
    RISC-V: add a definition for the SIE SEIE bit
    RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h
    RISC-V: simplify software interrupt / IPI code
    RISC-V: remove timer leftovers
    RISC-V: Add early printk support via the SBI console
    RISC-V: Don't increment sepc after breakpoint.
    RISC-V: implement __lshrti3.
    RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building the vDSO

    Linus Torvalds
     

14 Aug, 2018

1 commit

  • 13e091b6d   Merge branch 'x86-timers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip ... Browse Code »

    Pull x86 timer updates from Thomas Gleixner:
    "Early TSC based time stamping to allow better boot time analysis.

    This comes with a general cleanup of the TSC calibration code which
    grew warts and duct taping over the years and removes 250 lines of
    code. Initiated and mostly implemented by Pavel with help from various
    folks"

    * 'x86-timers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (37 commits)
    x86/kvmclock: Mark kvm_get_preset_lpj() as __init
    x86/tsc: Consolidate init code
    sched/clock: Disable interrupts when calling generic_sched_clock_init()
    timekeeping: Prevent false warning when persistent clock is not available
    sched/clock: Close a hole in sched_clock_init()
    x86/tsc: Make use of tsc_calibrate_cpu_early()
    x86/tsc: Split native_calibrate_cpu() into early and late parts
    sched/clock: Use static key for sched_clock_running
    sched/clock: Enable sched clock early
    sched/clock: Move sched clock initialization and merge with generic clock
    x86/tsc: Use TSC as sched clock early
    x86/tsc: Initialize cyc2ns when tsc frequency is determined
    x86/tsc: Calibrate tsc only once
    ARM/time: Remove read_boot_clock64()
    s390/time: Remove read_boot_clock64()
    timekeeping: Default boot time offset to local_clock()
    timekeeping: Replace read_boot_clock64() with read_persistent_wall_and_boot_offset()
    s390/time: Add read_persistent_wall_and_boot_offset()
    x86/xen/time: Output xen sched_clock time from 0
    x86/xen/time: Initialize pv xen time in init_hypervisor_platform()
    ...

    Linus Torvalds
     

13 Aug, 2018

1 commit

  • 62b019436   clocksource: new RISC-V SBI timer driver ... Browse Code »

    The RISC-V ISA defines a per-hart real-time clock and timer, which is
    present on all systems. The clock is accessed via the 'rdtime'
    pseudo-instruction (which reads a CSR), and the timer is set via an SBI
    call.

    Contains various improvements from Atish Patra .

    Signed-off-by: Dmitriy Cherkasov
    Signed-off-by: Palmer Dabbelt
    [hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(),
    minor cleanups, merged hotplug cpu support and other improvements
    from Atish]
    Signed-off-by: Christoph Hellwig
    Acked-by: Thomas Gleixner
    Reviewed-by: Atish Patra
    Signed-off-by: Palmer Dabbelt

    Palmer Dabbelt
     

02 Aug, 2018

2 commits

26 Jul, 2018

6 commits

20 Jul, 2018

1 commit

  • 227e3958a   ARM/time: Remove read_boot_clock64() ... Browse Code »

    read_boot_clock64() is deleted, and replaced with
    read_persistent_wall_and_boot_offset().

    The default implementation of read_persistent_wall_and_boot_offset()
    provides a better fallback than the current stubs for read_boot_clock64()
    that arm has with no users, so remove the old code.

    Signed-off-by: Pavel Tatashin
    Signed-off-by: Thomas Gleixner
    Cc: steven.sistare@oracle.com
    Cc: daniel.m.jordan@oracle.com
    Cc: linux@armlinux.org.uk
    Cc: schwidefsky@de.ibm.com
    Cc: heiko.carstens@de.ibm.com
    Cc: john.stultz@linaro.org
    Cc: sboyd@codeaurora.org
    Cc: hpa@zytor.com
    Cc: douly.fnst@cn.fujitsu.com
    Cc: peterz@infradead.org
    Cc: prarit@redhat.com
    Cc: feng.tang@intel.com
    Cc: pmladek@suse.com
    Cc: gnomes@lxorguk.ukuu.org.uk
    Cc: linux-s390@vger.kernel.org
    Cc: boris.ostrovsky@oracle.com
    Cc: jgross@suse.com
    Cc: pbonzini@redhat.com
    Link: https://lkml.kernel.org/r/20180719205545.16512-19-pasha.tatashin@oracle.com

    Pavel Tatashin
     

11 Jul, 2018

1 commit

  • 5e18e4129   clocksource: arm_arch_timer: Set arch_mem_timer cpumask to cpu_possible_mask ... Browse Code »

    Currently, arch_mem_timer cpumask is set to cpu_all_mask which should be
    fine. However, cpu_possible_mask is more accurate and if there are other
    clockevent source in the system which are set to cpu_possible_mask, then
    having cpu_all_mask may result in issue.

    E.g. on a platform with arm,sp804 timer with rating 300 and
    cpu_possible_mask and this arch_mem_timer timer with rating 400 and
    cpu_all_mask, tick_check_preferred may choose both preferred as the
    cpumasks are not equal though they must be.

    This issue was root caused incorrectly initially and a fix was merged as
    commit 1332a9055801 ("tick: Prefer a lower rating device only if it's CPU
    local device").

    Signed-off-by: Sudeep Holla
    Signed-off-by: Thomas Gleixner
    Tested-by: Kevin Hilman
    Tested-by: Martin Blumenstingl
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: Marc Zyngier
    Cc: Mark Rutland
    Link: https://lkml.kernel.org/r/1531151136-18297-2-git-send-email-sudeep.holla@arm.com

    Sudeep Holla
     

24 Jun, 2018

1 commit

  • 6242258b6   Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip ... Browse Code »

    Pull timer fixes from Thomas Gleixner:
    "A small set of fixes for time(r) related issues:

    - Fix a long standing conversion issue in jiffies_to_msecs() for odd
    HZ values like 1024 or 1200 which resulted in returning 0 for small
    jiffies values due to rounding down.

    - Use the proper CONFIG symbol in the new Y2038 safe compat code for
    posix-timers. Not yet a visible breakage, but this will immediately
    trigger when the architecture support for the new interfaces is
    merged.

    - Return an error code in the STM32 clocksource driver on failure
    instead of success.

    - Remove the redundant and stale irq disabled check in the posix cpu
    timer code. The check is at the wrong place anyway and lockdep
    already covers it via the sighand lock locking coverage"

    * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
    time: Make sure jiffies_to_msecs() preserves non-zero time periods
    posix-timers: Fix nanosleep_copyout() for CONFIG_COMPAT_32BIT_TIME
    clocksource/drivers/stm32: Fix error return code
    posix-cpu-timers: Remove lockdep_assert_irqs_disabled()

    Linus Torvalds
     

13 Jun, 2018

2 commits

  • 6396bb221   treewide: kzalloc() -> kcalloc() ... Browse Code »

    The kzalloc() function has a 2-factor argument form, kcalloc(). This
    patch replaces cases of:

    kzalloc(a * b, gfp)

    with:
    kcalloc(a * b, gfp)

    as well as handling cases of:

    kzalloc(a * b * c, gfp)

    with:

    kzalloc(array3_size(a, b, c), gfp)

    as it's slightly less ugly than:

    kzalloc_array(array_size(a, b), c, gfp)

    This does, however, attempt to ignore constant size factors like:

    kzalloc(4 * 1024, gfp)

    though any constants defined via macros get caught up in the conversion.

    Any factors with a sizeof() of "unsigned char", "char", and "u8" were
    dropped, since they're redundant.

    The Coccinelle script used for this was:

    // Fix redundant parens around sizeof().
    @@
    type TYPE;
    expression THING, E;
    @@

    (
    kzalloc(
    - (sizeof(TYPE)) * E
    + sizeof(TYPE) * E
    , ...)
    |
    kzalloc(
    - (sizeof(THING)) * E
    + sizeof(THING) * E
    , ...)
    )

    // Drop single-byte sizes and redundant parens.
    @@
    expression COUNT;
    typedef u8;
    typedef __u8;
    @@

    (
    kzalloc(
    - sizeof(u8) * (COUNT)
    + COUNT
    , ...)
    |
    kzalloc(
    - sizeof(__u8) * (COUNT)
    + COUNT
    , ...)
    |
    kzalloc(
    - sizeof(char) * (COUNT)
    + COUNT
    , ...)
    |
    kzalloc(
    - sizeof(unsigned char) * (COUNT)
    + COUNT
    , ...)
    |
    kzalloc(
    - sizeof(u8) * COUNT
    + COUNT
    , ...)
    |
    kzalloc(
    - sizeof(__u8) * COUNT
    + COUNT
    , ...)
    |
    kzalloc(
    - sizeof(char) * COUNT
    + COUNT
    , ...)
    |
    kzalloc(
    - sizeof(unsigned char) * COUNT
    + COUNT
    , ...)
    )

    // 2-factor product with sizeof(type/expression) and identifier or constant.
    @@
    type TYPE;
    expression THING;
    identifier COUNT_ID;
    constant COUNT_CONST;
    @@

    (
    - kzalloc
    + kcalloc
    (
    - sizeof(TYPE) * (COUNT_ID)
    + COUNT_ID, sizeof(TYPE)
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - sizeof(TYPE) * COUNT_ID
    + COUNT_ID, sizeof(TYPE)
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - sizeof(TYPE) * (COUNT_CONST)
    + COUNT_CONST, sizeof(TYPE)
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - sizeof(TYPE) * COUNT_CONST
    + COUNT_CONST, sizeof(TYPE)
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - sizeof(THING) * (COUNT_ID)
    + COUNT_ID, sizeof(THING)
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - sizeof(THING) * COUNT_ID
    + COUNT_ID, sizeof(THING)
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - sizeof(THING) * (COUNT_CONST)
    + COUNT_CONST, sizeof(THING)
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - sizeof(THING) * COUNT_CONST
    + COUNT_CONST, sizeof(THING)
    , ...)
    )

    // 2-factor product, only identifiers.
    @@
    identifier SIZE, COUNT;
    @@

    - kzalloc
    + kcalloc
    (
    - SIZE * COUNT
    + COUNT, SIZE
    , ...)

    // 3-factor product with 1 sizeof(type) or sizeof(expression), with
    // redundant parens removed.
    @@
    expression THING;
    identifier STRIDE, COUNT;
    type TYPE;
    @@

    (
    kzalloc(
    - sizeof(TYPE) * (COUNT) * (STRIDE)
    + array3_size(COUNT, STRIDE, sizeof(TYPE))
    , ...)
    |
    kzalloc(
    - sizeof(TYPE) * (COUNT) * STRIDE
    + array3_size(COUNT, STRIDE, sizeof(TYPE))
    , ...)
    |
    kzalloc(
    - sizeof(TYPE) * COUNT * (STRIDE)
    + array3_size(COUNT, STRIDE, sizeof(TYPE))
    , ...)
    |
    kzalloc(
    - sizeof(TYPE) * COUNT * STRIDE
    + array3_size(COUNT, STRIDE, sizeof(TYPE))
    , ...)
    |
    kzalloc(
    - sizeof(THING) * (COUNT) * (STRIDE)
    + array3_size(COUNT, STRIDE, sizeof(THING))
    , ...)
    |
    kzalloc(
    - sizeof(THING) * (COUNT) * STRIDE
    + array3_size(COUNT, STRIDE, sizeof(THING))
    , ...)
    |
    kzalloc(
    - sizeof(THING) * COUNT * (STRIDE)
    + array3_size(COUNT, STRIDE, sizeof(THING))
    , ...)
    |
    kzalloc(
    - sizeof(THING) * COUNT * STRIDE
    + array3_size(COUNT, STRIDE, sizeof(THING))
    , ...)
    )

    // 3-factor product with 2 sizeof(variable), with redundant parens removed.
    @@
    expression THING1, THING2;
    identifier COUNT;
    type TYPE1, TYPE2;
    @@

    (
    kzalloc(
    - sizeof(TYPE1) * sizeof(TYPE2) * COUNT
    + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
    , ...)
    |
    kzalloc(
    - sizeof(TYPE1) * sizeof(THING2) * (COUNT)
    + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
    , ...)
    |
    kzalloc(
    - sizeof(THING1) * sizeof(THING2) * COUNT
    + array3_size(COUNT, sizeof(THING1), sizeof(THING2))
    , ...)
    |
    kzalloc(
    - sizeof(THING1) * sizeof(THING2) * (COUNT)
    + array3_size(COUNT, sizeof(THING1), sizeof(THING2))
    , ...)
    |
    kzalloc(
    - sizeof(TYPE1) * sizeof(THING2) * COUNT
    + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
    , ...)
    |
    kzalloc(
    - sizeof(TYPE1) * sizeof(THING2) * (COUNT)
    + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
    , ...)
    )

    // 3-factor product, only identifiers, with redundant parens removed.
    @@
    identifier STRIDE, SIZE, COUNT;
    @@

    (
    kzalloc(
    - (COUNT) * STRIDE * SIZE
    + array3_size(COUNT, STRIDE, SIZE)
    , ...)
    |
    kzalloc(
    - COUNT * (STRIDE) * SIZE
    + array3_size(COUNT, STRIDE, SIZE)
    , ...)
    |
    kzalloc(
    - COUNT * STRIDE * (SIZE)
    + array3_size(COUNT, STRIDE, SIZE)
    , ...)
    |
    kzalloc(
    - (COUNT) * (STRIDE) * SIZE
    + array3_size(COUNT, STRIDE, SIZE)
    , ...)
    |
    kzalloc(
    - COUNT * (STRIDE) * (SIZE)
    + array3_size(COUNT, STRIDE, SIZE)
    , ...)
    |
    kzalloc(
    - (COUNT) * STRIDE * (SIZE)
    + array3_size(COUNT, STRIDE, SIZE)
    , ...)
    |
    kzalloc(
    - (COUNT) * (STRIDE) * (SIZE)
    + array3_size(COUNT, STRIDE, SIZE)
    , ...)
    |
    kzalloc(
    - COUNT * STRIDE * SIZE
    + array3_size(COUNT, STRIDE, SIZE)
    , ...)
    )

    // Any remaining multi-factor products, first at least 3-factor products,
    // when they're not all constants...
    @@
    expression E1, E2, E3;
    constant C1, C2, C3;
    @@

    (
    kzalloc(C1 * C2 * C3, ...)
    |
    kzalloc(
    - (E1) * E2 * E3
    + array3_size(E1, E2, E3)
    , ...)
    |
    kzalloc(
    - (E1) * (E2) * E3
    + array3_size(E1, E2, E3)
    , ...)
    |
    kzalloc(
    - (E1) * (E2) * (E3)
    + array3_size(E1, E2, E3)
    , ...)
    |
    kzalloc(
    - E1 * E2 * E3
    + array3_size(E1, E2, E3)
    , ...)
    )

    // And then all remaining 2 factors products when they're not all constants,
    // keeping sizeof() as the second factor argument.
    @@
    expression THING, E1, E2;
    type TYPE;
    constant C1, C2, C3;
    @@

    (
    kzalloc(sizeof(THING) * C2, ...)
    |
    kzalloc(sizeof(TYPE) * C2, ...)
    |
    kzalloc(C1 * C2 * C3, ...)
    |
    kzalloc(C1 * C2, ...)
    |
    - kzalloc
    + kcalloc
    (
    - sizeof(TYPE) * (E2)
    + E2, sizeof(TYPE)
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - sizeof(TYPE) * E2
    + E2, sizeof(TYPE)
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - sizeof(THING) * (E2)
    + E2, sizeof(THING)
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - sizeof(THING) * E2
    + E2, sizeof(THING)
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - (E1) * E2
    + E1, E2
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - (E1) * (E2)
    + E1, E2
    , ...)
    |
    - kzalloc
    + kcalloc
    (
    - E1 * E2
    + E1, E2
    , ...)
    )

    Signed-off-by: Kees Cook

    Kees Cook
     
  • a26ed66c2   clocksource/drivers/stm32: Fix error return code ... Browse Code »

    Return an error code on failure.

    Problem found using Coccinelle.

    Signed-off-by: Julia Lawall
    Signed-off-by: Thomas Gleixner
    Cc: Daniel Lezcano
    Cc: kernel-janitors@vger.kernel.org
    Cc: Maxime Coquelin
    Cc: Alexandre Torgue
    Cc: linux-arm-kernel@lists.infradead.org
    Link: https://lkml.kernel.org/r1528640655-18948-3-git-send-email-Julia.Lawall@lip6.fr

    Julia Lawall
     

10 Jun, 2018

1 commit

  • 6419945e3   Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux ... Browse Code »

    Pull clk updates from Stephen Boyd:
    "This time we have a good set of changes to the core framework that do
    some general cleanups, but nothing too major. The majority of the diff
    goes to two SoCs, Actions Semi and Qualcomm. A brand new driver is
    introduced for Actions Semi so it takes up some lines to add all the
    different types, and the Qualcomm diff is there because we add support
    for two SoCs and it's quite a bit of data.

    Otherwise the big driver updates are on TI Davinci and Amlogic
    platforms. And then the long tail of driver updates for various fixes
    and stuff follows after that.

    Core:
    - debugfs cleanups removing error checking and an unused provider API
    - Removal of a clk init typedef that isn't used
    - Usage of match_string() to simplify parent string name matching
    - OF clk helpers moved to their own file (linux/of_clk.h)
    - Make clk warnings more readable across kernel versions

    New Drivers:
    - Qualcomm SDM845 GCC and Video clk controllers
    - Qualcomm MSM8998 GCC
    - Actions Semi S900 SoC support
    - Nuvoton npcm750 microcontroller clks
    - Amlogic axg AO clock controller

    Removed Drivers:
    - Deprecated Rockchip clk-gate driver

    Updates:
    - debugfs functions stopped checking return values
    - Support for the MSIOF module clocks on Rensas R-Car M3-N
    - Support for the new Rensas RZ/G1C and R-Car E3 SoCs
    - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs
    - Berlin and Amlogic SPDX tagging
    - Usage of of_clk_get_parent_count() in more places
    - Proper implementation of the CDEV1/2 clocks on Tegra20
    - Allwinner H6 PRCM clock support and R40 EMAC support
    - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet
    - Round closest support for meson's mpll driver
    - Support for meson8b nand clocks and gxbb video decoder clocks
    - Mediatek mali clks
    - STM32MP1 fixes
    - Uniphier LD11/LD20 stream demux system clock"

    * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits)
    clk: qcom: Export clk_fabia_pll_configure()
    clk: bcm: Update and add Stingray clock entries
    dt-bindings: clk: Update Stingray binding doc
    clk-si544: Properly round requested frequency to nearest match
    clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
    clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
    clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
    clk: ingenic: jz4770: Change OTG from custom to standard gated clock
    clk: ingenic: Support specifying "wait for clock stable" delay
    clk: ingenic: Add support for clocks whose gate bit is inverted
    clk: use match_string() helper
    clk: bcm2835: use match_string() helper
    clk: Return void from debug_init op
    clk: remove clk_debugfs_add_file()
    clk: tegra: no need to check return value of debugfs_create functions
    clk: davinci: no need to check return value of debugfs_create functions
    clk: bcm2835: no need to check return value of debugfs_create functions
    clk: no need to check return value of debugfs_create functions
    clk: imx6: add EPIT clock support
    clk: mvebu: use correct bit for 98DX3236 NAND
    ...

    Linus Torvalds
     

23 May, 2018

4 commits

19 May, 2018

3 commits

02 May, 2018

1 commit