13 Feb, 2019
2 commits
-
[ Upstream commit 187fade88ca0ff2df9d360ca751d948d73db7095 ]
If mapping the CvP BAR fails, we still can configure the FPGA via
PCI config space access. In this case the iomap pointer is NULL.
On x86_64, passing NULL address to pci_iounmap() generates
"Bad IO access at port 0x0" output with stack call trace. Fix it.Signed-off-by: Anatolij Gustschin
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
Signed-off-by: Sasha Levin -
[ Upstream commit 68f60538daa4bc3da5d0764d46f391916fba20fd ]
The probe function needs to verify the CvP enable bit in order to
properly determine if FPGA Manager functionality can be safely
enabled.Fixes: 34d1dc17ce97 ("fpga manager: Add Altera CvP driver")
Signed-off-by: Andreas Puhm
Signed-off-by: Anatolij Gustschin
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
Signed-off-by: Sasha Levin
26 Jan, 2019
1 commit
-
[ Upstream commit 30522a951f9d02f261d0697c35cb42205b1fae17 ]
Currently registering CvP managers works only for first probed CvP
device, for all other devices it is refused due to duplicated chkcfg
sysfs entry:fpga_manager fpga3: Altera CvP FPGA Manager @0000:0c:00.0 registered
sysfs: cannot create duplicate filename '/bus/pci/drivers/altera-cvp/chkcfg'
CPU: 0 PID: 3808 Comm: bash Tainted: G O 4.19.0-custom+ #5
Call Trace:
dump_stack+0x46/0x5b
sysfs_warn_dup+0x53/0x60
sysfs_add_file_mode_ns+0x16d/0x180
sysfs_create_file_ns+0x51/0x60
altera_cvp_probe+0x16f/0x2a0 [altera_cvp]
local_pci_probe+0x3f/0xa0
? pci_match_device+0xb1/0xf0
pci_device_probe+0x116/0x170
really_probe+0x21b/0x2c0
driver_probe_device+0x4b/0xe0
bind_store+0xcb/0x130
kernfs_fop_write+0xfd/0x180
__vfs_write+0x21/0x150
? selinux_file_permission+0xdc/0x130
vfs_write+0xa8/0x1a0
? find_vma+0xd/0x60
ksys_write+0x3d/0x90
do_syscall_64+0x44/0xf0
entry_SYSCALL_64_after_hwframe+0x44/0xa9
...
altera-cvp 0000:0c:00.0: Can't create sysfs chkcfg file
fpga_manager fpga3: fpga_mgr_unregister Altera CvP FPGA Manager @0000:0c:00.0Move chkcfg creation to module init as suggested by Alan.
Signed-off-by: Anatolij Gustschin
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
Signed-off-by: Sasha Levin
30 Sep, 2018
2 commits
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fpga_bridge_dev_match() returns a FPGA bridge struct, not a
FPGA manager struct so s/manager/bridge/.Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
A couple drivers were accessing the region struct after it had been
freed. Save off the pointer to the mgr before the region struct gets
freed.Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman
12 Sep, 2018
1 commit
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In case of error, the function dfl_fme_create_region() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check should
be replaced with IS_ERR().Fixes: 29de76240e86 ("fpga: dfl: fme: add partial reconfiguration sub feature support")
Signed-off-by: Wei Yongjun
Acked-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
16 Jul, 2018
1 commit
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We want the char-misc fixes in here as well.
Signed-off-by: Greg Kroah-Hartman
15 Jul, 2018
25 commits
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DMA memory regions are required for Accelerated Function Unit (AFU) usage.
These two ioctls allow user space applications to map user memory regions
for dma, and unmap them after use. Iova is returned from driver to user
space application via DFL_FPGA_PORT_DMA_MAP ioctl. Application needs to
unmap it after use, otherwise, driver will unmap them in device file
release operation.Each AFU has its own rb tree to keep track of its mapped DMA regions.
Ioctl interfaces:
* DFL_FPGA_PORT_DMA_MAP
Do the dma mapping per user_addr and length provided by user.
Return iova in provided struct dfl_fpga_port_dma_map.* DFL_FPGA_PORT_DMA_UNMAP
Unmap the dma region per iova provided by user.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
User Accelerated Function Unit sub feature exposes the MMIO region of
the AFU. After valid PR bitstream is programmed and the port is enabled,
then this MMIO region could be accessed.This patch adds support to enumerate the AFU MMIO region and expose it
to userspace via mmap file operation. Below interfaces are exposed to user:Sysfs interface:
* /sys/class/fpga_region///afu_id
Read-only. Indicate which PR bitstream is programmed to this AFU.Ioctl interfaces:
* DFL_FPGA_PORT_GET_INFO
Provide info to userspace on the number of supported region.
Only UAFU region is supported now.* DFL_FPGA_PORT_GET_REGION_INFO
Provide region information, including access permission, region size,
offset from the start of device fd.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common
ones which need to be supported by all feature devices drivers including
FME and AFU. This patch implements above 2 ioctls in FPGA Accelerated
Function Unit (AFU) driver.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
The port header register set is always present for port, it is mainly
for capability, control and status of the ports that AFU connected to.This patch implements header sub feature support. Below user interfaces
are created by this patch.Sysfs interface:
* /sys/class/fpga_region///id
Read-only. Port ID.Ioctl interface:
* DFL_FPGA_PORT_RESET
Reset the FPGA Port and its AFU.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This patch registers the port ops into the global list in the DFL
framework, and it allows other modules to use the port ops. And
This patch includes the implementation of the get_id and enable_set
ops too.Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
On DFL FPGA devices, the Accelerated Function Unit (AFU), can be
reprogrammed for different functions. It connects to the FPGA
infrastructure (static FPGA region) via a Port. Port CSRs are
implemented separately from the AFU CSRs to provide control and
status of the Port. Once valid PR bitstream is programmed into
the AFU, it allows access to the AFU CSRs in the AFU MMIO space.This patch only implements basic driver framework for AFU, including
device file operation framework.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This patch adds compat_id support, it reuses fme manager's
compat id, as the per region compat id is actually from the
fme manager's register.Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds fpga region platform driver for FPGA Management Engine.
It register an fpga region with given fpga manager / bridge device.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds fpga bridge platform driver for FPGA Management Engine.
It implements the enable_set callback for fpga bridge.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds compat_id support to fme manager driver, it
reads the ID from the hardware register. And it could be used
for compatibility check before partial reconfiguration.Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds fpga manager driver for FPGA Management Engine (FME). It
implements fpga_manager_ops for FPGA Partial Reconfiguration function.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Partial Reconfiguration (PR) is the most important function for FME. It
allows reconfiguration for given Port/Accelerated Function Unit (AFU).It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges,
and invokes fpga-region's interface (fpga_region_program_fpga) for PR
operation once PR request received via ioctl. Below user space interface
is exposed by this sub feature.Ioctl interface:
* DFL_FPGA_FME_PORT_PR
Do partial reconfiguration per information from userspace, including
target port(AFU), buffer size and address info. It returns error code
to userspace if failed. For detailed PR error information, user needs
to read fpga-mgr's status sysfs interface.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common
ones which need to be supported by all feature devices drivers including
FME and AFU. Userspace application can use these ioctl interfaces to get
the API info and check if specific extension is supported or not in
current driver.This patch implements above 2 ioctls in FPGA Management Engine (FME)
driver.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
The Header Register set is always present for FPGA Management Engine (FME),
this patch implements init and uinit function for header sub feature and
introduces several read-only sysfs interfaces for the capability and
status.Sysfs interfaces:
* /sys/class/fpga_region///ports_num
Read-only. Number of ports implemented* /sys/class/fpga_region///bitstream_id
Read-only. Bitstream (static FPGA region) identifier number. It contains
the detailed version and other information of this static FPGA region.* /sys/class/fpga_region///bitstream_metadata
Read-only. Bitstream (static FPGA region) meta data. It contains the
synthesis date, seed and other information of this static FPGA region.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
The FPGA Management Engine (FME) provides power, thermal management,
performance counters, partial reconfiguration and other functions. For each
function, it is packaged into a private feature linked to the FME feature
device in the 'Device Feature List'. It's a platform device created by
DFL framework.This patch adds the basic framework of FME platform driver. It defines
sub feature drivers to handle the different sub features, including init,
uinit and ioctl. It also registers the file operations for the device file.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
The Device Feature List (DFL) is implemented in MMIO and features
are linked via the DFLs. This patch enables pcie driver to prepare
enumeration information (e.g. locations of all device feature lists
in MMIO) and use common APIs provided by the Device Feature List
framework to enumerate each feature device linked.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Zhang Yi
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This patch implements the basic framework of the driver for FPGA PCIe
device which implements the Device Feature List (DFL) in its MMIO space.
This driver is verified on Intel(R) PCIe-based FPGA DFL devices, including
both integrated (e.g. Intel Server Platform with In-package FPGA) and
discrete (e.g. Intel FPGA PCIe Acceleration Cards) solutions.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Zhang Yi
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds one common function in DFL framework. It uses
port_ops get_id callback to get port id and compare it with given
value. This function could be used as match function of the
dfl_fpga_cdev_find_port function.Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
In some cases, other DFL driver modules may need to access some port
operations, e.g. disable / enable port for partial reconfiguration in
FME module. In order to avoid dependency between port and FME modules,
this patch introduces the dfl_fpga_port_ops support in DFL framework.
A global dfl_fpga_port_ops list is added in the DFL framework, and
it allows other DFL modules to use these port operations registered
to this list, even in virtualization case, the port platform device
is turned into VF / guest VM and hidden in host, the registered
port_ops is still usable. It resolves the dependency issues between
modules, but once get port ops API returns a valid port ops, that
means related port driver module has been module_get to prevent from
unexpected unload, and put port ops API must be invoked after use.These APIs introduced by this patch is listed below:
* dfl_fpga_port_ops_add
add one port ops to the global list.* dfl_fpga_port_ops_del
del one port ops from the global list.* dfl_fpga_port_ops_get / dfl_fpga_port_ops_put
get/put the port ops before/after use.Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This patch abstracts the common operations of the sub features and defines
the feature_ops data structure, including init, uinit and ioctl function
pointers. And this patch adds some common helper functions for FME and AFU
drivers, e.g. dfl_feature_dev_use_begin/end which are used to ensure
exclusive usage of the feature device file.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
Signed-off-by: Zhang Yi
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
For feature devices, we need a method to find the port dedicated
to the device. This patch adds a function dfl_fpga_cdev_find_port
for this purpose. e.g. FPGA Management Engine (FME) Partial
Reconfiguration sub feature, it uses this function to find
dedicated port on the device for PR function implementation.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
For feature devices drivers, both the FPGA Management Engine (FME) and
Accelerated Function Unit (AFU) driver need to expose user interfaces via
the device file, for example, mmap and ioctls.This patch adds chardev support in the dfl driver for feature devices,
FME and AFU. It reserves the chardev regions for FME and AFU and provide
interfaces for FME and AFU driver to register their device file operations.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Zhang Yi
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Device Feature List (DFL) defines a feature list structure that creates
a linked list of feature headers within the MMIO space to provide an
extensible way of adding features. This patch introduces a kernel module
to provide basic infrastructure to support FPGA devices which implement
the Device Feature List.Usually there will be different features and their sub features linked into
the DFL. This code provides common APIs for feature enumeration, it creates
a container device (FPGA base region), walks through the DFLs and creates
platform devices for feature devices (Currently it only supports two
different feature devices, FPGA Management Engine (FME) and Port which
the Accelerator Function Unit (AFU) connected to). In order to enumerate
the DFLs, the common APIs required low level driver to provide necessary
enumeration information (e.g. address for each device feature list for
given device) and fill it to the dfl_fpga_enum_info data structure. Please
refer to below description for APIs added for enumeration.Functions for enumeration information preparation:
*dfl_fpga_enum_info_alloc
allocate enumeration information data structure.*dfl_fpga_enum_info_add_dfl
add a device feature list to dfl_fpga_enum_info data structure.*dfl_fpga_enum_info_free
free dfl_fpga_enum_info data structure and related resources.Functions for feature device enumeration:
*dfl_fpga_feature_devs_enumerate
enumerate feature devices and return container device.*dfl_fpga_feature_devs_remove
remove feature devices under given container device.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Zhang Yi
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This patch introduces a compat_id pointer member and sysfs interface
for each fpga region, similar as compat_id for fpga manager, it allows
applications to read the per region compat_id for compatibility
checking before other actions on this fpga-region (e.g. PR).Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds status sysfs interface for fpga manager, it's a
read only interface which allows user to get fpga manager status,
including full/partial reconfiguration error and other status
information. It adds a status callback to fpga_manager_ops too,
allows each fpga_manager driver to define its own method to
collect latest status from hardware.The following sysfs file is created:
* /sys/class/fpga_manager//status
Return status of fpga manager, including reconfiguration errors.Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman
07 Jul, 2018
1 commit
-
If 'fpga_mgr_create()' fails, we should release some resources, as done
in the other error handling path of the function.Fixes: 7085e2a94f7d ("fpga: manager: change api, don't use drvdata")
Signed-off-by: Christophe JAILLET
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
26 May, 2018
7 commits
-
The following functions also free the struct. Add that
fact to the function documentation.
- fpga_mgr_free
- fpga_bridge_free
- fpga_region_freeSigned-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Fix formatting and some cleanup for the kernel-doc documentation in
fpga-region.cSigned-off-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
Fix the following warnings when documentation is built:
./drivers/fpga/fpga-bridge.c:143: warning: Function parameter or
member 'info' not described in 'fpga_bridge_get'./drivers/fpga/fpga-bridge.c:1: warning: no structured comments found
Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
Clean up the kernel-doc documentation in fpga-mgr.c and fix the
following warnings when documentation is built:./drivers/fpga/fpga-mgr.c:252: warning: Function parameter or member
'info' not described in 'fpga_mgr_buf_load'./drivers/fpga/fpga-mgr.c:252: warning: Excess function parameter
'flags' description in 'fpga_mgr_buf_load'Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
Replace GPLv2 boilerplate with SPDX in FPGA code that came from me or
from Altera.Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Add fpga_region_create/free API functions.
Change fpga_region_register to take FPGA region struct as the only
parameter. Change fpga_region_unregister to return void.struct fpga_region *fpga_region_create(struct device *dev,
struct fpga_manager *mgr,
int (*get_bridges)(struct fpga_region *));
void fpga_region_free(struct fpga_region *region);
int fpga_region_register(struct fpga_region *region);
void fpga_region_unregister(struct fpga_region *region);Remove groups storage from struct fpga_region, it's not
needed. Callers can just "region->dev.groups = groups;"
after calling fpga_region_create.Update the drivers that call fpga_region_register with the new API.
Signed-off-by: Alan Tull
Signed-off-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
Change fpga_bridge_register to not set drvdata. This is to support
the case where a PCIe device can have more than one bridge.Add API functions to create/free the fpga bridge struct. Change
fpga_bridge_register/unregister to take FPGA bridge struct as
the only parameter.struct fpga_bridge
*fpga_bridge_create(struct device *dev, const char *name,
const struct fpga_bridge_ops *br_ops,
void *priv);
void fpga_bridge_free(struct fpga_bridge *br);
int fpga_bridge_register(struct fpga_bridge *br);
void fpga_bridge_unregister(struct fpga_bridge *br);Update the drivers that call fpga_bridge_register with the new API.
Signed-off-by: Alan Tull
Reported-by: Jiuyue Ma
Signed-off-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman