23 Jul, 2019
3 commits
-
Fix below build warning when CONFIG_PM_SLEEP=n:
drivers/pinctrl/freescale/pinctrl-imx8mn.c:355:12: warning:
‘imx8mn_pinctrl_suspend’ defined but not used [-Wunused-function]
static int imx8mn_pinctrl_suspend(struct device *dev)
^
drivers/pinctrl/freescale/pinctrl-imx8mn.c:360:12: warning:
‘imx8mn_pinctrl_resume’ defined but not used [-Wunused-function]
static int imx8mn_pinctrl_resume(struct device *dev)
^Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai
(cherry picked from commit 6f84c2d2d1e30d8f3cf68245fa1f12dfac8b6a8e) -
Fix below build warning when CONFIG_PM_SLEEP=n:
drivers/pinctrl/freescale/pinctrl-imx8mm.c:355:12: warning:
‘imx8mm_pinctrl_suspend’ defined but not used [-Wunused-function]
static int imx8mm_pinctrl_suspend(struct device *dev)
^
drivers/pinctrl/freescale/pinctrl-imx8mm.c:361:12: warning:
‘imx8mm_pinctrl_resume’ defined but not used [-Wunused-function]
static int imx8mm_pinctrl_resume(struct device *dev)
^Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai
(cherry picked from commit a4745f292da5bcaae3d75e3ac8b293c71fe7dcb1) -
Fix below build warning when CONFIG_PM_SLEEP=n:
drivers/pinctrl/freescale/pinctrl-imx7d.c:400:12: warning:
'imx7d_pinctrl_resume' defined but not used [-Wunused-function]
static int imx7d_pinctrl_resume(struct device *dev)
^~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/freescale/pinctrl-imx7d.c:394:12: warning:
'imx7d_pinctrl_suspend' defined but not used [-Wunused-function]static int imx7d_pinctrl_suspend(struct device *dev)
^~~~~~~~~~~~~~~~~~~~~Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai
(cherry picked from commit 219d360b02f74e210c8382de5c8061d660b14241)
27 Jun, 2019
1 commit
-
Add new SoC i.MX8MN pinctrl driver support.
Signed-off-by: Bai Ping
Signed-off-by: Anson Huang
Reviewed-by: Abel Vesa
Reviewed-by: Bai Ping
18 Apr, 2019
17 commits
-
Copy from rel_imx_4.14.98_2.0.0_ga_rc1
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
Signed-off-by: Leonard Crestez -
Copy pin header from rel_imx_4.14.98_2.0.0_ga_rc1 and enable
compilation. The C code of the driver was already accepted in v4.19 in
an acceptable form so we use that.Signed-off-by: Anson Huang
Signed-off-by: Leonard Crestez -
Copy from rel_imx_4.14.98_2.0.0_ga_rc1
Signed-off-by: Anson Huang
Signed-off-by: Leonard Crestez -
Copy from rel_imx_4.14.98_2.0.0_ga_rc1 and add minor build fix in
pinctrl-scu.Signed-off-by: Peng Fan
Signed-off-by: Anson Huang
Signed-off-by: Leonard Crestez -
Fix compilation warnings by removing unused variables and adding missed
qualifiers.Signed-off-by: Arulpandiyan Vadivel
-
Pinctrl support of a device tree property "pinctrl-assert-gpios"
under client device node to select function at a board level pin
multiplexer. The pin route is controlled by a GPIO or i2c/spi expander
GPIO.For i2c/spi expander GPIO, it may be loaded after client device that
set "pinctrl-assert-gpios" property in devicetree. Then the client device's
pin function doesn't work.So it should add defer probe check for the GPIO pin.
Acked-by: Leonard Crestez
Signed-off-by: Fugang Duan
Signed-off-by: Arulpandiyan Vadivel -
First of all, the design of using CONFIG_IBE_OBE is wrong as both VF and
IMX has IBE and OBE while current code defined it in common code but for
only IMX which causes a bit confusing.Second, remove the following invalid comments as we will clear IBE.
"IBE always enabled allows us to read the value on the wire"Last, replace the complicated "if else" statement with a much simpler one.
Cc: Bai Ping
Reviewed-by: Peng Fan
Reviewed-by: Fugang Duan
Fixes: 07787c40ff3b ("MLK-13485-3 pinctrl: imx: modify the imx pinctrl to support imx7ulp gpio")
Signed-off-by: Dong Aisheng
Signed-off-by: Arulpandiyan Vadivel -
As i.MX8MQ is a ARM64 SoC but it does NOT use SCU pinctrl, so
need to support both SCU and MEMMAP pinctrl together for ARM64
build.use IMX8_USE_SCU flag to distinguish SCU and MEMMAP pinctrl
type.Signed-off-by: Anson Huang
Signed-off-by: Peng Fan
[Arul: Fix merge conflicts]
Signed-off-by: Arulpandiyan Vadivel -
switch to use new format. Split mux out from pad config.
Change the high two bits in pad config to 0, because driver
will automatically set that two bits to 1.Signed-off-by: Peng Fan
[Arul: Fix merge conflicts, Skipped arm64 dts files]
Signed-off-by: Arulpandiyan Vadivel -
list is a local variable, each time imx_pinctrl_parse_pin is
invoked, list points to the first pin. Directly use list_p in
imx_pinctrl_parse_pin to fix it.When splitting pinctrl-imx.c, two pieces code is correctly moved.
- In imx_pmx_set_one_pin, when mux_reg is -1, need to return 0 to
let the caller continue the loop.
- In imx_pinctrl_parse_pin, need to use (mux_reg != -1) when calculating
the pin_id.Signed-off-by: Peng Fan
[Arul: Fix merge conflicts]
Signed-off-by: Arulpandiyan Vadivel -
On i.MX8QM/QXP, pin is handled by SCU, A53/72 can not directly
handle pinmux as i.MX6/7.Split the original pinctrl-imx.c to two parts, the pinctrl-memmap.c
will handle the memory mapped access for i.MX6/7. pinctrl-imx.c
will be shared by legacy i.mx and i.MX8.Introduce pinctrl-scu.c to handle the connection with SCU to configure
pin settings.Signed-off-by: Peng Fan
Signed-off-by: Anson HuangRebased on top of 4.14 changes
Signed-off-by: Leonard Crestez
[Arul: Fix merge conflicts]
Signed-off-by: Arulpandiyan Vadivel -
This makes imx7ulp boot.
Signed-off-by: Leonard Crestez
Signed-off-by: Arulpandiyan Vadivel -
Add support for imx7ulp iomux controller.
Signed-off-by: Fugang Duan
Merged with upstream 4.14 version
Signed-off-by: Leonard Crestez
[Arul: Fix merge conflicts]
Signed-off-by: Arulpandiyan Vadivel -
Add pinctrl driver support for i.MX6SLL.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
[Arul: Fix merge conficts]
Signed-off-by: Arulpandiyan Vadivel -
On i.MX6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL register
have been moved from IOMUXC to IOMUXC_SNVS, so the pinctrl driver
should be modified to support the IOMUXC_SNVS.Signed-off-by: Bai Ping
[Arul: Fix merge conflicts]
Signed-off-by: Arulpandiyan Vadivel -
To support pinctl hog restore after LPSR resume back,
add suspend/resume in pinctrl driver.Signed-off-by: Robin Gong
[Arul: Fix merge conflicts]
Signed-off-by: Arulpandiyan Vadivel -
It's pretty common that on some reference design or validation boards,
one pin could be used by two devices on board, and the pin route is
controlled by a GPIO. So to assert the pin for given device, not only
the pinmux controller in SoC needs to be set up properly but also the
GPIO needs to be pulled up/down.The patch adds support of a device tree property "pinctrl-assert-gpios"
under client device node. It plays pretty much like a board level pin
multiplexer, and steers the pin route by controlling the GPIOs. When
client device has the property represent in its node, pinctrl device
tree mapping function will firstly pull up/down the GPIOs to assert the
pins for the device at board level.[shawn.guo: cherry-pick commit e5a718edab82 from imx_3.10.y]
Signed-off-by: Shawn Guo
Signed-off-by: Arulpandiyan Vadivel
06 Apr, 2019
1 commit
-
[ Upstream commit 6daae00243e622dd3feec7965bfe421ad6dd317e ]
Gigabit Ethernet requires the Ethernet TXD0..3 and RXD0..3 data lines.
Add the missing eth_rxd2 and eth_rxd3 definitions so we don't have to
rely on the bootloader to set them up correctly.The vendor u-boot sources for Odroid-C1 use the following Ethernet
pinmux configuration:
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f);
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000);
This translates to the following pin groups in the mainline kernel:
- register 6 bit 0: eth_rxd1 (DIF_0_P)
- register 6 bit 1: eth_rxd0 (DIF_0_N)
- register 6 bit 2: eth_rx_dv (DIF_1_P)
- register 6 bit 3: eth_rx_clk (DIF_1_N)
- register 6 bit 6: eth_tx_en (DIF_3_P)
- register 6 bit 8: eth_ref_clk (DIF_3_N)
- register 6 bit 9: eth_mdc (DIF_4_P)
- register 6 bit 10: eth_mdio_en (DIF_4_N)
- register 6 bit 11: eth_tx_clk (GPIOH_9)
- register 6 bit 12: eth_txd2 (GPIOH_8)
- register 6 bit 13: eth_txd3 (GPIOH_7)
- register 7 bit 20: eth_txd0_0 (GPIOH_6)
- register 7 bit 21: eth_txd1_0 (GPIOH_5)
- register 7 bit 22: eth_rxd3 (DIF_2_P)
- register 7 bit 23: eth_rxd2 (DIF_2_N)All functions except eth_rxd2 and eth_rxd3 are already supported by the
pinctrl-meson8b driver.Suggested-by: Jianxin Pan
Signed-off-by: Martin Blumenstingl
Reviewed-by: Kevin Hilman
Tested-by: Emiliano Ingrassia
Reviewed-by: Emiliano Ingrassia
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin
24 Mar, 2019
1 commit
-
[ Upstream commit c17abcfa93bf0be5e48bb011607d237ac2bfc839 ]
Fix the mismatch between the "sdxc_d13_1_a" pin group definition from
meson8b_cbus_groups and the entry in sdxc_a_groups ("sdxc_d0_13_1_a").
This makes it possible to use "sdxc_d13_1_a" in device-tree files to
route the MMC data 1..3 pins to GPIOX_1..3.Fixes: 0fefcb6876d0d6 ("pinctrl: Add support for Meson8b")
Signed-off-by: Martin Blumenstingl
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin
14 Mar, 2019
1 commit
-
[ Upstream commit f165988b77ef849eb0c1aebd94fe778024f88314 ]
Fixes issue created by 9b3e4207661e67f04c72af15e29f74cd944f5964.
It wasn't possible for one_regmap_config to be non-NULL at the point
it was tested for mcp23s18 devices.Applied the same pattern of allocating one_regmap_config using
devm_kmemdump() and then initializing the local regmap structure
from that.Signed-off-by: Jason Kridner
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin
27 Feb, 2019
1 commit
-
commit 1f60652dd586d1b3eee7c4602892a97a62fa937a upstream.
Clang warns when one enumerated type is implicitly converted to another:
drivers/pinctrl/pinctrl-max77620.c:56:12: warning: implicit conversion
from enumeration type 'enum max77620_pinconf_param' to different
enumeration type 'enum pin_config_param' [-Wenum-conversion]
.param = MAX77620_ACTIVE_FPS_SOURCE,
^~~~~~~~~~~~~~~~~~~~~~~~~~It is expected that pinctrl drivers can extend pin_config_param because
of the gap between PIN_CONFIG_END and PIN_CONFIG_MAX so this conversion
isn't an issue. Most drivers that take advantage of this define the
PIN_CONFIG variables as constants, rather than enumerated values. Do the
same thing here so that Clang no longer warns.Link: https://github.com/ClangBuiltLinux/linux/issues/139
Signed-off-by: Nathan Chancellor
Signed-off-by: Linus Walleij
Signed-off-by: Greg Kroah-Hartman
15 Feb, 2019
2 commits
-
commit e3f72b749da2bf63bed7409e416f160418d475b6 upstream.
Well, hopefully 3rd time is a charm. We tried making that check
DMI_BIOS_VERSION and DMI_BOARD_VERSION, but the real one is
DMI_PRODUCT_VERSION.Fixes: 86c5dd6860a6 ("pinctrl: cherryview: limit Strago DMI workarounds to version 1.0")
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=197953
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1631930
Cc: stable@vger.kernel.org
Signed-off-by: Dmitry Torokhov
Reviewed-by: Andy Shevchenko
Acked-by: Mika Westerberg
Signed-off-by: Linus Walleij
Signed-off-by: Greg Kroah-Hartman -
commit 10098709b4ee6f6f19f25ba81d9c6f83518c584c upstream.
The H6 main pin controller has four banks of interrupt-triggering pins.
The driver as originally submitted only specified three, but had pin
descriptions referencing a fourth bank. This results in a out-of-bounds
access into .irq_array of struct sunxi_pinctrl. This however did not
result in a crash until v4.20, with commit a66d972465d1 ("devres: Align
data[] to ARCH_KMALLOC_MINALIGN"), which changed the alignment of memory
region returned by devm_kcalloc(). The increase likely moved the
out-of-bounds access into the next, unmapped page.With KASAN on, the bug is quite clear:
BUG: KASAN: slab-out-of-bounds in sunxi_pinctrl_init_with_variant+0x49c/0x12b8
Write of size 4 at addr ffff80002c680280 by task swapper/0/1CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.0.0-rc1-00016-gc480a5e6a077 #3
Hardware name: OrangePi Lite2 (DT)
Call trace:
dump_backtrace+0x0/0x220
show_stack+0x14/0x20
dump_stack+0xac/0xd4
print_address_description+0x60/0x25c
kasan_report+0x14c/0x1ac
__asan_store4+0x80/0xa0
sunxi_pinctrl_init_with_variant+0x49c/0x12b8
h6_pinctrl_probe+0x18/0x20
platform_drv_probe+0x6c/0xc8
really_probe+0x244/0x4b0
driver_probe_device.part.4+0x11c/0x164
__driver_attach+0x120/0x190
bus_for_each_dev+0xe8/0x158
driver_attach+0x30/0x40
bus_add_driver+0x308/0x318
driver_register+0xbc/0x1d0
__platform_driver_register+0x7c/0x88
h6_pinctrl_driver_init+0x18/0x20
do_one_initcall+0xd4/0x208
kernel_init_freeable+0x230/0x2c8
kernel_init+0x10/0x108
ret_from_fork+0x10/0x1cAllocated by task 1:
kasan_kmalloc.part.0+0x4c/0x100
kasan_kmalloc+0xc4/0xe8
kasan_slab_alloc+0x14/0x20
__kmalloc_track_caller+0x130/0x238
devm_kmalloc+0x34/0xd0
sunxi_pinctrl_init_with_variant+0x1d8/0x12b8
h6_pinctrl_probe+0x18/0x20
platform_drv_probe+0x6c/0xc8
really_probe+0x244/0x4b0
driver_probe_device.part.4+0x11c/0x164
__driver_attach+0x120/0x190
bus_for_each_dev+0xe8/0x158
driver_attach+0x30/0x40
bus_add_driver+0x308/0x318
driver_register+0xbc/0x1d0
__platform_driver_register+0x7c/0x88
h6_pinctrl_driver_init+0x18/0x20
do_one_initcall+0xd4/0x208
kernel_init_freeable+0x230/0x2c8
kernel_init+0x10/0x108
ret_from_fork+0x10/0x1cFreed by task 0:
(stack is not available)The buggy address belongs to the object at ffff80002c680080
which belongs to the cache kmalloc-512 of size 512
The buggy address is located 0 bytes to the right of
512-byte region [ffff80002c680080, ffff80002c680280)
The buggy address belongs to the page:
page:ffff7e0000b1a000 count:1 mapcount:0 mapping:ffff80002e00c780 index:0xffff80002c683c80 compound_mapcount: 0
flags: 0x10200(slab|head)
raw: 0000000000010200 ffff80002e003a10 ffff80002e003a10 ffff80002e00c780
raw: ffff80002c683c80 0000000000100001 00000001ffffffff 0000000000000000
page dumped because: kasan: bad access detectedMemory state around the buggy address:
ffff80002c680180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ffff80002c680200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>ffff80002c680280: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
^
ffff80002c680300: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
ffff80002c680380: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fcCorrect the number of IRQ banks so there are no more mismatches.
Fixes: c8a830904991 ("pinctrl: sunxi: add support for the Allwinner H6 main pin controller")
Cc:
Signed-off-by: Chen-Yu Tsai
Tested-by: Neil Armstrong
Acked-by: Maxime Ripard
Signed-off-by: Linus Walleij
Signed-off-by: Greg Kroah-Hartman
13 Feb, 2019
4 commits
-
[ Upstream commit 2b745ac3cceb8fc1d9985990c8241a821ea97e53 ]
The GPIOAO pins (as well as the two exotic GPIO_BSD_EN and GPIO_TEST_N)
only belong to the pin controller in the AO domain. With the current
definition these pins cannot be referred to in .dts files as group
(which is possible on GXBB and GXL for example).Add a separate "gpio_aobus" function to fix the mapping between the pin
controller and the GPIO pins in the AO domain. This is similar to how
the GXBB and GXL drivers implement this functionality.Fixes: 9dab1868ec0db4 ("pinctrl: amlogic: Make driver independent from two-domain configuration")
Signed-off-by: Martin Blumenstingl
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin -
[ Upstream commit 42f9b48cc5402be11d2364275eb18c257d2a79e8 ]
The GPIOAO pins (as well as the two exotic GPIO_BSD_EN and GPIO_TEST_N)
only belong to the pin controller in the AO domain. With the current
definition these pins cannot be referred to in .dts files as group
(which is possible on GXBB and GXL for example).Add a separate "gpio_aobus" function to fix the mapping between the pin
controller and the GPIO pins in the AO domain. This is similar to how
the GXBB and GXL drivers implement this functionality.Fixes: 9dab1868ec0db4 ("pinctrl: amlogic: Make driver independent from two-domain configuration")
Signed-off-by: Martin Blumenstingl
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin -
[ Upstream commit a9d9f6b83f1bb05da849b3540e6d1f70ef1c2343 ]
devm_kstrdup() may return NULL if internal allocation failed.
Thus using label, name is unsafe without checking. Therefor
in the unlikely case of allocation failure, sx150x_probe() simply
returns -ENOMEM.Signed-off-by: Nicholas Mc Guire
Fixes: 9e80f9064e73 ("pinctrl: Add SX150X GPIO Extender Pinctrl Driver")
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin -
[ Upstream commit 3c7b30f704b6f5e53eed6bf89cf2c8d1b38b02c0 ]
The BCM2835 pinctrl driver acquires a spinlock in its ->irq_enable,
->irq_disable and ->irq_set_type callbacks. Spinlocks become sleeping
locks with CONFIG_PREEMPT_RT_FULL=y, therefore invocation of one of the
callbacks in atomic context may cause a hard lockup if at least two GPIO
pins in the same bank are used as interrupts. The issue doesn't occur
with just a single interrupt pin per bank because the lock is never
contended. I'm experiencing such lockups with GPIO 8 and 28 used as
level-triggered interrupts, i.e. with ->irq_disable being invoked on
reception of every IRQ.The critical section protected by the spinlock is very small (one bitop
and one RMW of an MMIO register), hence converting to a raw spinlock
seems a better trade-off than converting the driver to threaded IRQ
handling (which would increase latency to handle an interrupt).Cc: Mathias Duckeck
Signed-off-by: Lukas Wunner
Acked-by: Julia Cartwright
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin
13 Jan, 2019
1 commit
-
[ Upstream commit 614b1868a125a0ba24be08f3a7fa832ddcde6bca ]
We just changed the code so we apply bias disable on the correct
register but forgot to align the register calculation. The result
is that we apply the change on the correct register, but possibly
at the incorrect offset/bitThis went undetected because offsets tends to be the same between
REG_PULL and REG_PULLEN for a given pin the EE controller. This
is not true for the AO controller.Fixes: e39f9dd8206a ("pinctrl: meson: fix pinconf bias disable")
Signed-off-by: Jerome Brunet
Acked-by: Neil Armstrong
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin
20 Dec, 2018
1 commit
-
commit 478b6767ad26ab86d9ecc341027dd09a87b1f997 upstream.
Pin PH11 is used on various A83T board to detect a change in the OTG
port's ID pin, as in when an OTG host cable is plugged in.The incorrect offset meant the gpiochip/irqchip was activating the wrong
pin for interrupts.Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller support")
Cc:
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
Signed-off-by: Linus Walleij
Signed-off-by: Greg Kroah-Hartman
01 Dec, 2018
5 commits
-
[ Upstream commit a1705f02704cd8a24d434bfd0141ee8142ad277a ]
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconfFixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b")
Signed-off-by: Jerome Brunet
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin -
[ Upstream commit e91b162d2868672d06010f34aa83d408db13d3c6 ]
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconfFixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Jerome Brunet
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin -
[ Upstream commit ed3a2b74f3eb34c84c8377353f4730f05acdfd05 ]
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconfFixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions")
Signed-off-by: Jerome Brunet
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin -
[ Upstream commit 4bc51e1e350cd4707ce6e551a93eae26d40b9889 ]
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconfFixes: 468c234f9ed7 ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC")
Signed-off-by: Jerome Brunet
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin -
[ Upstream commit e39f9dd8206ad66992ac0e6218ef1ba746f2cce9 ]
If a bias is enabled on a pin of an Amlogic SoC, calling .pin_config_set()
with PIN_CONFIG_BIAS_DISABLE will not disable the bias. Instead it will
force a pull-down bias on the pin.Instead of the pull type register bank, the driver should access the pull
enable register bank.Fixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Jerome Brunet
Acked-by: Neil Armstrong
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin
14 Nov, 2018
2 commits
-
[ Upstream commit b432414b996d32a1bd9afe2bd595bd5729c1477f ]
If you look at "pinconf-groups" in debugfs for ssbi-gpio you'll notice
it looks like nonsense.The problem is fairly well described in commit 1cf86bc21257 ("pinctrl:
qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliant") and
commit 05e0c828955c ("pinctrl: msm: Fix msm_config_group_get() to be
compliant"), but it was pointed out that ssbi-gpio has the same
problem. Let's fix it there too.Fixes: b4c45fe974bc ("pinctrl: qcom: ssbi: Family A gpio & mpp drivers")
Signed-off-by: Douglas Anderson
Reviewed-by: Stephen Boyd
Reviewed-by: Bjorn Andersson
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman -
[ Upstream commit 0d5b476f8f57fcb06c45fe27681ac47254f63fd2 ]
If you look at "pinconf-groups" in debugfs for ssbi-mpp you'll notice
it looks like nonsense.The problem is fairly well described in commit 1cf86bc21257 ("pinctrl:
qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliant") and
commit 05e0c828955c ("pinctrl: msm: Fix msm_config_group_get() to be
compliant"), but it was pointed out that ssbi-mpp has the same
problem. Let's fix it there too.NOTE: in case it's helpful to someone reading this, the way to tell
whether to do the -EINVAL or not is to look at the PCONFDUMP for a
given attribute. If the last element (has_arg) is false then you need
to do the -EINVAL trick.ALSO NOTE: it seems unlikely that the values returned when we try to
get PIN_CONFIG_BIAS_PULL_UP will actually be printed since "has_arg"
is false for that one, but I guess it's still fine to return different
values so I kept doing that. It seems like another driver (ssbi-gpio)
uses a custom attribute (PM8XXX_QCOM_PULL_UP_STRENGTH) for something
similar so maybe a future change should do that here too.Fixes: cfb24f6ebd38 ("pinctrl: Qualcomm SPMI PMIC MPP pin controller driver")
Signed-off-by: Douglas Anderson
Reviewed-by: Stephen Boyd
Reviewed-by: Bjorn Andersson
Signed-off-by: Linus Walleij
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
