31 Mar, 2011
1 commit
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Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi
13 Oct, 2007
1 commit
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Allow for configuration of the processor ID for the simplar non-MMU
ARM parts.Signed-off-by: Greg Ungerer
Signed-off-by: Russell King
28 Sep, 2006
1 commit
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All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:Related operation Safe condition
a. any CP15 access !CPU_CP15
b. alignment trap CPU_CP15_MMU
c. D-cache(C-bit) CPU_CP15
d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
CPU_ARM720 || CPU_ARM740 ||
CPU_XSCALE || CPU_XSC3 )
e. alternate vector CPU_CP15 && !CPU_ARM740
f. TTB CPU_CP15_MMU
g. Domain CPU_CP15_MMU
h. FSR/FAR CPU_CP15_MMUFor example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.Signed-off-by: Hyok S. Choi
Signed-off-by: Russell King
27 Mar, 2006
2 commits
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The high page vector (0xFFFF0000) does not supported in nommu mode.
This patch allows the vectors to be 0x00000000 or the begining of DRAM
in nommu mode.Signed-off-by: Hyok S. Choi
Signed-off-by: Russell King -
This patch adds Kconfig-nommu for noMMU specific configurations
and MMUEXT variable into Makefile.Signed-off-by: Hyok S. Choi
Signed-off-by: Russell King