26 Oct, 2010
2 commits
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When using CP15 cache operations (c7), we make sure that Rd (r0)
is actually 0 as ARM 926 TRM is saying.Signed-off-by: Nicolas Ferre
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For power management at91_pm_enter() routine, use the cpu_do_idle() for a
rock solid "wait for interrupt" implementation.
For AT91SAM9 ARM 926 based chips, we can exceed the cache line length as
we can access RAM even while in self-refresh mode.
We keep plain access to CP15 for at91rm9200 as this feature is not
available: instructions have to be in a single cache line.Signed-off-by: Nicolas Ferre
09 Jul, 2010
1 commit
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This rework allows to address tow memory controllers. AT91SAM9263 and
AT91SAM9G45 family have tow SDRAM or DDR/SDRAM controllers. Power management
should take care of this.
This patch modify the way RAM IP header files are implemented to allow
access to registers of both controllers ; it also adds some macros.We also modify the power management files to use those modified header files.
Slow clock (assembly) and regular power management functions are synchronized
for setting of RAM self-refresh procedure:
(lpr & ~AT91_DDRSDRC_LPCB) | AT91_DDRSDRC_LPCB_SELF_REFRESHNote that AT91RM9200 is not impacted by this modification.
Signed-off-by: Nicolas Ferre
Acked-by: Andrew Victor
Signed-off-by: Russell King
11 Nov, 2009
1 commit
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This patch adds the support for cpuidle on AT91 SoCs, taken from the
cpuidle support in mach-kirkwood.
cpuidle needs sdram_selfrefresh_enable and _disable, so move their
definition to a separate header file instead of duplicating the code
already used in pm.c.Tested-by: Nicolas Ferre
Signed-off-by: Albin Tonnerre
Acked-by: Andrew Victor
Signed-off-by: Russell King
