20 Dec, 2011
1 commit
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* picoxcell/cleanup: (4 commits)
MAINTAINERS: add maintainer entry for Picochip picoxcell
ARM: picoxcell: move io mappings to common.c
ARM: picoxcell: don't reserve irq_descs
ARM: picoxcell: remove mach/memory.hConflicts:
arch/arm/mach-at91/setup.c
28 Nov, 2011
3 commits
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we will select now the DBGU used by the soc at Kconfig level
For the DEBUG_LL and early_printk this will allow to select which DBGU to use
this will also allow to select them when multiple SOC are enabledSigned-off-by: Jean-Christophe PLAGNIOL-VILLARD
Acked-by: Nicolas Ferre -
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Acked-by: Nicolas Ferre -
this will allow to ioremap the register of the PIT, PMC and others
and make the code soc independentSigned-off-by: Jean-Christophe PLAGNIOL-VILLARD
Acked-by: Nicolas Ferre
16 Nov, 2011
1 commit
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A generic version should replace this later.
Signed-off-by: Nicolas Pitre
28 Jul, 2011
7 commits
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre
Cc: Patrice Vilchez -
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre
Cc: Patrice Vilchez -
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre
Cc: Patrice Vilchez -
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre
Cc: Patrice Vilchez -
instead of reading the registers everytime
the current implementation respect the following constrain:
- allow 1 to n soc to be enabled
- allow to have a virtual cpu type and subtype
- always detect the cpu type and subtype and report it
- detect if the soc support is enabled
- prepare for sysfs export support
- drop soc specific code via compiler when the soc not enabled
(via cpu_is_xxx)Today if we read the exid we will have the same value for 9g35 and 9m11
and we will need to check the cidr toowith the new implementation we just need to check the soc subtype
this will also allow to have specific virtual subtype for rm9200 which the
board will have to specify via at91rm9200_set_type(int) as we have no way to
detect it.this implementation is inspired by the SH cpu detection support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre
Cc: Patrice Vilchez -
they are the same except the default priority
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre
Cc: Patrice Vilchez -
On all at91 except rm9200 and x40 have the System Controller starts
at address 0xffffc000 and has a size of 16KiB.On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting
at 0xfffff000This patch removes the individual definitions of AT91_BASE_SYS and
replaces them with a common version at base 0xfffffc000 and size 16KiB
and map the same memory spaceSigned-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre
Cc: Patrice Vilchez