10 Jan, 2012

1 commit

  • New feature development

    This adds support for new features, and contains stuff from most
    platforms. A number of these patches could have fit into other
    branches, too, but were small enough not to cause too much
    confusion here.

    * tag 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits)
    mfd/db8500-prcmu: remove support for early silicon revisions
    ARM: ux500: fix the smp_twd clock calculation
    ARM: ux500: remove support for early silicon revisions
    ARM: ux500: update register files
    ARM: ux500: register DB5500 PMU dynamically
    ARM: ux500: update ASIC detection for U5500
    ARM: ux500: support DB8520
    ARM: picoxcell: implement watchdog restart
    ARM: OMAP3+: hwmod data: Add the default clockactivity for I2C
    ARM: OMAP3: hwmod data: disable multiblock reads on MMC1/2 on OMAP34xx/35xx <= ES2.1
    ARM: OMAP: USB: EHCI and OHCI hwmod structures for OMAP4
    ARM: OMAP: USB: EHCI and OHCI hwmod structures for OMAP3
    ARM: OMAP: hwmod data: Add support for AM35xx UART4/ttyO3
    ARM: Orion: Remove address map info from all platform data structures
    ARM: Orion: Get address map from plat-orion instead of via platform_data
    ARM: Orion: mbus_dram_info consolidation
    ARM: Orion: Consolidate the address map setup
    ARM: Kirkwood: Add configuration for MPP12 as GPIO
    ARM: Kirkwood: Recognize A1 revision of 6282 chip
    ARM: ux500: update the MOP500 GPIO assignments
    ...

    Linus Torvalds
     

05 Jan, 2012

1 commit


14 Dec, 2011

2 commits


17 May, 2011

6 commits


04 Mar, 2011

1 commit


06 Nov, 2009

1 commit


23 May, 2009

1 commit


22 May, 2009

1 commit


24 Apr, 2009

1 commit

  • Symbols like SOFT_RESET are way too generic to be exported at large.
    To avoid this, let's move the mbus bridge register defines into a
    separate file and include it where needed. This affects mach-kirkwood,
    mach-loki, mach-mv78xx0 and mach-orion5x simultaneously as they all
    share code in plat-orion which relies on those defines.

    Some other defines have been moved to narrower scopes, or simply deleted
    when they had no user.

    This fixes compilation problem with mpt2sas on the above listed
    platforms.

    Signed-off-by: Nicolas Pitre
    Signed-off-by: Russell King

    Nicolas Pitre
     

04 Mar, 2009

1 commit


20 Feb, 2009

2 commits


04 Dec, 2008

1 commit


12 Oct, 2008

1 commit

  • * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
    [ARM] 5300/1: fixup spitz reset during boot
    [ARM] 5295/1: make ZONE_DMA optional
    [ARM] 5239/1: Palm Zire 72 power management support
    [ARM] 5298/1: Drop desc_handle_irq()
    [ARM] 5297/1: [KS8695] Fix two compile-time warnings
    [ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
    [ARM] pxa: allow multi-machine PCMCIA builds
    [ARM] pxa: add preliminary CPUFREQ support for PXA3xx
    [ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
    [ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
    [ARM] pxa/zylonite: add support for USB OHCI
    [ARM] ohci-pxa27x: use ioremap() and offset for register access
    [ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
    [ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
    [ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
    [ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
    [ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
    [ARM] pxa: simplify DMA register definitions
    [ARM] pxa: make additional DCSR bits valid for PXA3xx
    [ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
    ...

    Fixed up conflicts in
    arch/arm/mach-versatile/core.c
    sound/soc/pxa/pxa2xx-ac97.c
    sound/soc/pxa/pxa2xx-i2s.c
    manually.

    Linus Torvalds
     

26 Sep, 2008

1 commit


05 Sep, 2008

1 commit


09 Aug, 2008

1 commit


07 Aug, 2008

1 commit


23 Jun, 2008

1 commit

  • The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
    (depending on the model) one or two Feroceon CPU cores with 512K of L2
    cache and VFP coprocessors running at (depending on the model) between
    800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
    interfaces that can each run either in x4 or quad x1 mode, three USB
    2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
    TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
    interface, four UARTs, and depending on the model, two or four gigabit
    ethernet interfaces.

    This patch adds basic support for the platform, and allows booting
    on the MV78x00 development board, with functional UARTs, SATA, PCIe,
    GigE and USB ports.

    Signed-off-by: Stanislav Samsonov
    Signed-off-by: Lennert Buytenhek

    Stanislav Samsonov