30 Jun, 2011
2 commits
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Move the saving of the auxiliary control registers into C; there's
no need for this to be in assembly code. This results in less
assembly code to deal with in OMAP.Kevin tested full-chip retention and off on 3430/n900, 3530/Overo and
3630/Zoom3.Tested-by: Kevin Hilman
Signed-off-by: Russell King -
Most of the ASM sleep code (in arch/arm/mach-omap2/sleep34xx.S)
is copied to internal SRAM at boot and after wake-up from CORE OFF
mode. However only a small part of the code really needs to run from
internal SRAM.This fix lets most of the ASM idle code run from the DDR in order to
minimize the SRAM usage and the overhead in the code copy.The only pieces of code that are mandatory in SRAM are:
- the i443 erratum WA,
- the i581 erratum WA,
- the security extension code.SRAM usage:
- original code:
. 560 bytes for omap3_sram_configure_core_dpll (used by DVFS),
. 852 bytes for omap_sram_idle (used by suspend/resume in RETention),
. 124 bytes for es3_sdrc_fix (used by suspend/resume in OFF mode on ES3.x),
. 108 bytes for save_secure_ram_context (used on HS parts only).With this fix the usage for suspend/resume in RETention goes down 288
bytes, so the gain in SRAM usage for suspend/resume is 564 bytes.Also fixed the SRAM initialization sequence to avoid an unnecessary
copy to SRAM at boot time and for readability.Tested on Beagleboard (ES2.x) in idle with full RET and OFF modes.
Kevin Hilman tested retention and off on 3430/n900, 3530/Overo and
3630/Zoom3Signed-off-by: Jean Pihet
Reviewed-by: Kevin Hilman
Tested-by: Kevin Hilman
Signed-off-by: Russell King
24 Jun, 2011
4 commits
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Upon return from off-mode, the ROM code jumps to a restore function
saved in the scratchpad. Based on SoC revision or errata, this
restore entry point is different. Current code uses some helper
functions in sleep34xx.S (get_*_restore_pointer) to get the restore
function entry point.When returning from off-mode, this code is executed from SDRAM, so
there's no reason to use these helper functions when using the SDRAM
entry points directly would work just fine.This patch uses ENTRY/ENDPROC to create "real" entry points for these
functions, and uses those values directly when writing the scratchpad.Tested all three entry points
- restore_es3: 3430/n900
- restore_3630: 3630/Zoom3
- restore: 3530/OveroSuggested-by: Russell King
Acked-by: Jean Pihet
Acked-by: Santosh Shilimkar
Signed-off-by: Kevin Hilman
Signed-off-by: Russell King -
Convert omap34xx to use the generic CPU suspend/resume support, rather
than implementing its own version. Tested on 3430 LDP.Reviewed-by: Kevin Hilman
Tested-by: Kevin Hilman
Acked-by: Jean Pihet
Signed-off-by: Russell King -
The code alludes to r9 being used to indicate what was lost over the
suspend/resume transition. However, although r9 is set, it is never
actually used.Also, the comments before the code (which refer to the value of r9)
and the comments against the assignment of r9 contradict each other,
so just remove them to avoid confusion.Reviewed-by: Kevin Hilman
Tested-by: Kevin Hilman
Acked-by: Jean Pihet
Signed-off-by: Russell King -
The ABI allows called functions to corrupt r0-r3 and ip (r12). So
its pointless saving these registers in the suspend code - the
calling function will expect them to be corrupted and so won't rely
on their contents after resume.Reviewed-by: Kevin Hilman
Tested-by: Kevin Hilman
Acked-by: Jean Pihet
Signed-off-by: Russell King
18 Mar, 2011
1 commit
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* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (258 commits)
omap: zoom: host should not pull up wl1271's irq line
arm: plat-omap: iommu: fix request_mem_region() error path
OMAP2+: Common CPU DIE ID reading code reads wrong registers for OMAP4430
omap4: mux: Remove duplicate mux modes
omap: iovmm: don't check 'da' to set IOVMF_DA_FIXED flag
omap: iovmm: disallow mapping NULL address when IOVMF_DA_ANON is set
omap2+: mux: Fix compile when CONFIG_OMAP_MUX is not selected
omap4: board-omap4panda: Initialise the serial pads
omap3: board-3430sdp: Initialise the serial pads
omap4: board-4430sdp: Initialise the serial pads
omap2+: mux: Add macro for configuring static with omap_hwmod_mux_init
omap2+: mux: Remove the use of IDLE flag
omap2+: Add separate list for dynamic pads to mux
perf: add OMAP support for the new power events
OMAP4: Add IVA OPP enteries.
OMAP4: Update Voltage Rail Values for MPU, IVA and CORE
OMAP4: Enable 800 MHz and 1 GHz MPU-OPP
OMAP3+: OPP: Replace voltage values with Macros
OMAP3: wdtimer: Fix CORE idle transition
Watchdog: omap_wdt: add fine grain runtime-pm
...Fix up various conflicts in
- arch/arm/mach-omap2/board-omap3evm.c
- arch/arm/mach-omap2/clock3xxx_data.c
- arch/arm/mach-omap2/usb-musb.c
- arch/arm/plat-omap/include/plat/usb.h
- drivers/usb/musb/musb_core.h
11 Mar, 2011
5 commits
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On the newer ARM processors like CortexA8, CortexA9, the caches can be
speculatively loaded while they are getting flushed.Clear the SCTLR C bit to prevent further data cache allocation as
part of cache clean routineSigned-off-by: Santosh Shilimkar
Signed-off-by: Kevin Hilman -
The current code saves few un-necessary registers which are read-only or
write-only, unused CP15 registers.Remove them and keep only necessary CP15 registers part of
low power context save/restore.Signed-off-by: Santosh Shilimkar
Signed-off-by: Kevin Hilman -
When L1 cache is suppose to be lost, it needs to be cleaned before
entrering to the low power mode.While at this, also fix few comments and remove un-necessary
clean_l2 lable.Signed-off-by: Santosh Shilimkar
Signed-off-by: Kevin Hilman -
Add necessary barriers after enabling MMU. Also use the sane way to
load pc and jump to it instead of executing ldma first up.Signed-off-by: Santosh Shilimkar
Signed-off-by: Kevin Hilman -
On ARMv7 dsb, dmb instructions are supported and can be used directly
instead of their cp15 equivalnet. Also remove the opcodes for smc
and use the available instruction directly in OMAP3 low power asm codeSigned-off-by: Santosh Shilimkar
Signed-off-by: Kevin Hilman
10 Mar, 2011
2 commits
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* Build unconditionally as ARM for correct interoperation with
OMAP firmware.* Fix an out-of-range ADR when building for ARM.
* Remove deprecated PC-relative stores.
* Add the required ENDPROC() directive for each ENTRY().
* .align before data words.
* Handle non-interworking return from v7_flush_dcache_all.
Signed-off-by: Dave Martin
Signed-off-by: Kevin Hilman -
For various reasons, Linux now only officially supports being built
with tools which are new enough to understand the SMC instruction.Replacing the hand-encoded instructions when the mnemonic also
allows for correct assembly in Thumb-2 (otherwise, the result is
random data in the middle of the code).The Makefile already ensures that this file is built with a high
enough gcc -march= flag (armv7-a).Signed-off-by: Dave Martin
Tested-by: Santosh Shilimkar
Tested-by: Jean Pihet
Signed-off-by: Kevin Hilman
04 Feb, 2011
1 commit
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The new fncpy API is better suited* for copying some
code to SRAM at runtime. This patch changes the ad-hoc
code to the more generic fncpy API.*: 1. fncpy ensures that the thumb mode bit is propagated,
2. fncpy provides the security of type safety between the
original function and the sram function pointer.Tested OK on OMAP3 in low power modes (RET/OFF)
using omap2plus_defconfig with !CONFIG_THUMB2_KERNEL.
Compile tested on OMAP1/2 using omap1_defconfig.Boot tested on OMAP1 & OMAP2
Tested OK with suspend/resume on OMAP2420/n810Boots fine on osk5912 and n800
Signed-off-by: Jean Pihet
Acked-by: Kevin Hilman
Acked-by: Tony Lindgren
Reviewed-by: Dave Martin
Tested-by: Kevin Hilman
Tested-by: Tony Lindgren
Signed-off-by: Russell King
22 Dec, 2010
12 commits
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In preparation for adding OMAP4-specific PRCM accessor/mutator
functions, split the existing OMAP2/3 PRCM code into OMAP2/3-specific
files. Most of what was in mach-omap2/{cm,prm}.{c,h} has now been
moved into mach-omap2/{cm,prm}2xxx_3xxx.{c,h}, since it was
OMAP2xxx/3xxx-specific.This process also requires the #includes in each of these files to be
changed to reference the new file name. As part of doing so, add some
comments into plat-omap/sram.c and plat-omap/mcbsp.c, which use
"sideways includes", to indicate that these users of the PRM/CM includes
should not be doing so.Thanks to Felipe Contreras for comments on this
patch.Signed-off-by: Paul Walmsley
Cc: Jarkko Nikula
Cc: Peter Ujfalusi
Cc: Liam Girdwood
Cc: Omar Ramirez Luna
Acked-by: Omar Ramirez Luna
Cc: Felipe Contreras
Acked-by: Felipe Contreras
Cc: Greg Kroah-Hartman
Acked-by: Mark Brown
Reviewed-by: Kevin Hilman
Tested-by: Kevin Hilman
Tested-by: Rajendra Nayak
Tested-by: Santosh Shilimkar -
Cosmetic fixes to the code:
- white spaces and tabs,
- alignement,
- comments rephrase and typos,
- multi-line commentsTested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.Signed-off-by: Jean Pihet
Acked-by: Santosh Shilimkar
Tested-by: Nishanth Menon
Signed-off-by: Kevin Hilman -
Errata covered:
- 1.157 & 1.185
- i443
- i581Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.Signed-off-by: Jean Pihet
Acked-by: Santosh Shilimkar
Tested-by: Nishanth Menon
Signed-off-by: Kevin Hilman -
- Reworked and simplified the execution paths for better
readability and to avoid duplication of code,
- Added comments on the entry and exit points and the interaction
with the ROM code for OFF mode restore,
- Reworked the existing comments for better readability.Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.Signed-off-by: Jean Pihet
Acked-by: Santosh Shilimkar
Tested-by: Nishanth Menon
Signed-off-by: Kevin Hilman -
Organize the code in the following sections:
- register access macros,
- API functions,
- internal functions.Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.Signed-off-by: Jean Pihet
Acked-by: Santosh Shilimkar
Tested-by: Nishanth Menon
Signed-off-by: Kevin Hilman -
Using macros from existing include files for registers addresses.
Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.Based on original patch from Vishwa.
Signed-off-by: Jean Pihet
Cc: Vishwanath BS
Acked-by: Santosh Shilimkar
Tested-by: Nishanth Menon
Signed-off-by: Kevin Hilman -
The SRAM PA addresses are locally defined and used at
different places, i.e. SRAM management code and idle sleep code.The macros are now defined at a centralized place, for
easier maintenance.Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.Signed-off-by: Jean Pihet
Acked-by: Santosh Shilimkar
Tested-by: Nishanth Menon
Signed-off-by: Kevin Hilman -
Remove unused code:
- macros,
- variables,
- unused semaphore locking API. This API shall be added back
when needed,
- infinite loops for debug.Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.Signed-off-by: Jean Pihet
Acked-by: Santosh Shilimkar
Reviewed-by: Nishanth Menon
Tested-by: Nishanth Menon
Signed-off-by: Kevin Hilman -
While coming out of MPU OSWR/OFF states, L2 controller is reseted.
The reset behavior is implementation specific as per ARMv7 TRM and
hence $L2 needs to be invalidated before it's use. Since the
AUXCTRL register is also reconfigured, disable L2 cache before
invalidating it and re-enables it afterwards. This is as per
Cortex-A8 ARM documentation.
Currently this is identified as being needed on OMAP3630 as the
disable/enable is done from "public side" while, on OMAP3430, this
is done in the "secure side".Cc: Kevin Hilman
Cc: Tony LindgrenAcked-by: Jean Pihet
Acked-by: Santosh Shilimkar[nm@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630]
Signed-off-by: Nishanth Menon
Signed-off-by: Eduardo Valentin
Signed-off-by: Peter 'p2' De Schrijver
Signed-off-by: Kevin Hilman -
Erratum id: i608
RTA (Retention Till Access) feature is not supported and leads to device
stability issues when enabled. This impacts modules with embedded memories
on OMAP3630Workaround is to disable RTA on boot and coming out of core off.
For disabling RTA coming out of off mode, we do this by overriding the
restore pointer for 3630 as the first point of entry before caches are
touched and is common for GP and HS devices. To disable earlier than
this could be possible by modifying the PPA for HS devices, but not for
GP devices.Cc: Kevin Hilman
Cc: Tony LindgrenAcked-by: Jean Pihet
Acked-by: Santosh Shilimkar[ambresh@ti.com: co-developer]
Signed-off-by: Ambresh K
Signed-off-by: Nishanth Menon
Signed-off-by: Kevin Hilman -
Erratum i581 impacts OMAP3 platforms.
PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing
the DPLL not to be locked at times.IMPORTANT:
*) This is not a complete workaround implementation as recommended
by the silicon erratum. This is a support logic for detecting lockups and
attempting to recover where possible and is known to provide stability
in multiple platforms.
*) This code is mostly important for inactive and retention. The ROM code
waits for the maximum DLL lock time when resuming from off mode. So for
off mode this code isn't really needed.
*) counters are introduced here for eventual export to userspace once the
cleanups are completed.This should eventually get refactored as part of cleanups to sleep34xx.S
Cc: Kevin Hilman
Cc: Tony LindgrenSigned-off-by: Peter 'p2' De Schrijver
Signed-off-by: Kevin Hilman -
Analysis in TI kernel with ETM showed that using cache mapped flush
in kernel instead of SO mapped flush cost drops by 65% (3.39mS down
to 1.17mS) for clean_l2 which is used during sleep sequences.
Overall:
- speed up
- unfortunately there isn't a good alternative flush method today
- code reduction and less maintenance and potential bug in
unmaintained codeThis also fixes the bug with the clean_l2 function usage.
Reported-by: Tony Lindgren
Cc: Kevin Hilman
Cc: Tony LindgrenAcked-by: Santosh Shilimkar
Acked-by: Jean Pihet[nm@ti.com: ported rkw's proposal to 2.6.37-rc2]
Signed-off-by: Nishanth Menon
Signed-off-by: Richard Woodruff
Signed-off-by: Kevin Hilman
09 Oct, 2010
1 commit
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Only OMAP2+ platforms have the System Control Module (SCM) IP block.
In the past, we've kept the SCM header file in plat-omap. This has
led to abuse - device drivers including it; includes being added that
create implicit dependencies on OMAP2+ builds; etc.In response, move the SCM headers into mach-omap2/.
As part of this, remove the direct SCM access from the OMAP UDC
driver. It was clearly broken. The UDC code needs an indepth review for
use on OMAP2+ chips.Signed-off-by: Paul Walmsley
Cc: Cory Maccarrone
Cc: Kyungmin Park
17 Jun, 2010
1 commit
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Signed-off-by: Uwe Kleine-König
Signed-off-by: Jiri Kosina
24 Feb, 2010
2 commits
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This patch adds a save and restore mechanism for ARM L2 auxiliary control
register. The feature is enabled by default for GP devices, but for HS/EMU
devices the user must enable the service and define the PPA service ID to
be used for setting L2 aux ctrl, as this is not currently supported by the
bootloader. If nobody alters the contents of L2 aux ctrl from its reset
value, this feature is not needed.Kconfig option to enable HS/EMU L2 aux save and restore:
- OMAP3_L2_AUX_SECURE_SAVE_RESTORE
Kconfig option to select HS/EMU PPA service for setting L2 aux ctrl:
- OMAP3_L2_AUX_SECURE_SERVICE_SET_IDSigned-off-by: Tero Kristo
Signed-off-by: Kevin Hilman -
This patch implements locking using the semaphore in scratchpad
memory preventing any concurrent access to scratchpad from OMAP
and Baseband/Modem processor.Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
27 Jan, 2010
1 commit
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Module offsets were same for OMAP2 and OMAP3 while they differ for OMAP4.
Hence we need different macros for identifying platform specific offsets.Signed-off-by: Abhijit Pagare
Signed-off-by: Paul Walmsley
Cc: Benoit Cousson
Cc: Rajendra Nayak
21 Jan, 2010
1 commit
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Current value is stored on SDRAM and it is written back during wakeup.
Previously a static value of 0x72 was written there.Signed-off-by: Tero Kristo
Acked-by: Thara Gopinath
Signed-off-by: Kevin Hilman
12 Nov, 2009
5 commits
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This patch improves the wakeup SRAM code polling the SDRC to become ready
instead of just waiting for a fixed amount of time.Signed-off-by: Peter 'p2' De Schrijver
Signed-off-by: Kevin Hilman -
Errata: ES3.0, ES3.1 SDRC not sending auto-refresh when OMAP wakes-up
from OFF modeSigned-off-by: Tero Kristo
Signed-off-by: Kalle Jokiniemi
Signed-off-by: Kevin Hilman -
The secure sram context save uses dma channels 0 and 1.
In order to avoid collision between kernel DMA transfers and
ROM code dma transfers, we need to reserve DMA channels 0
1 on high security devices.A bug in ROM code leaves dma irq status bits uncleared.
Hence those irq status bits need to be cleared when restoring
DMA context after off mode.There was also a faulty parameter given to PPA in the secure
ram context save assembly code, which caused interrupts to
be enabled during secure ram context save. This caused the
save to fail sometimes, which resulted the saved context
to be corrupted, but also left DMA channels in secure mode.
The secure mode DMA channels caused "DMA secure error with
device 0" errors to be displayed.Signed-off-by: Kalle Jokiniemi
Signed-off-by: Jouni Hogander
Signed-off-by: Kevin Hilman -
For HS/EMU devices, some additional resources need to be
saved/restored for off-mode support. Namely, saving the secure RAM
and a pointer to it in the scratchpad.Signed-off-by: Tero Kristo
Signed-off-by: Kevin Hilman -
Adds a 'save_state' option when calling into SRAM idle function
and adds some minor cleanups of SRAM asm code.Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
21 Oct, 2009
1 commit
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Move the remaining headers under plat-omap/include/mach
to plat-omap/include/plat. Also search and replace the
files using these headers to include using the right path.This was done with:
#!/bin/bash
mach_dir_old="arch/arm/plat-omap/include/mach"
plat_dir_new="arch/arm/plat-omap/include/plat"
headers=$(cd $mach_dir_old && ls *.h)
omap_dirs="arch/arm/*omap*/ \
drivers/video/omap \
sound/soc/omap"
other_files="drivers/leds/leds-ams-delta.c \
drivers/mfd/menelaus.c \
drivers/mfd/twl4030-core.c \
drivers/mtd/nand/ams-delta.c"for header in $headers; do
old="#include
29 May, 2009
1 commit
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This patch is to sync the core linux-omap PM code with mainline. This
code has evolved and been used for a while the linux-omap tree, but
the attempt here is to finally get this into mainline.Following this will be a series of patches from the 'PM branch' of the
linux-omap tree to add full PM hardware support from the linux-omap
tree.Much of this PM core code was written by Jouni Hogander with
significant contributions from Paul Walmsley as well as many others
from Nokia, Texas Instruments and linux-omap community.Signed-off-by: Jouni Hogander
Cc: Paul Walmsley
Signed-off-by: Kevin Hilman
