21 Feb, 2011

1 commit

  • The frequency memory bus on Tegra can be adjusted without
    disabling accesses to memory by updating the memory
    configuration registers from a per-board table, and then
    changing the clock frequency. The clock controller and
    memory controller have an interlock that prevents the
    new memory registers from taking effect until the
    clock frequency change.

    Acked-by: Olof Johansson
    Signed-off-by: Colin Cross

    Colin Cross