Eric Lee / smarc-fsl-linux-kernel

06 Dec, 2011

1 commit

07 Jul, 2011

1 commit

31 Mar, 2011

1 commit

23 Feb, 2011

1 commit

  • f6b0fa02e   ARM: pm: add generic CPU suspend/resume support ... Browse Code »

    This adds core support for saving and restoring CPU coprocessor
    registers for suspend/resume support. This contains support for suspend
    with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.
    Tested on Assabet and Tegra 2.

    Tested-by: Colin Cross
    Tested-by: Kukjin Kim
    Signed-off-by: Russell King

    Russell King
     

28 Oct, 2010

1 commit

  • c8c90860c   ARM: 6466/1: implement flush_icache_all for the rest of the CPUs ... Browse Code »

    Commit 81d11955bf0 ("ARM: 6405/1: Handle __flush_icache_all for
    CONFIG_SMP_ON_UP") added a new function to struct cpu_cache_fns:
    flush_icache_all(). It also implemented this for v6 and v7 but not
    for v5 and backwards. Without the function pointer in place, we
    will be calling wrong cache functions.

    For example with ep93xx we get following:

    Unable to handle kernel paging request at virtual address ee070f38
    pgd = c0004000
    [ee070f38] *pgd=00000000
    Internal error: Oops: 80000005 [#1] PREEMPT
    last sysfs file:
    Modules linked in:
    CPU: 0 Not tainted (2.6.36+ #1)
    PC is at 0xee070f38
    LR is at __dma_alloc+0x11c/0x2d0
    pc : [] lr : [] psr: 60000013
    sp : c581bde0 ip : 00000000 fp : c0472000
    r10: c0472000 r9 : 000000d0 r8 : 00020000
    r7 : 0001ffff r6 : 00000000 r5 : c0472400 r4 : c5980000
    r3 : c03ab7e0 r2 : 00000000 r1 : c59a0000 r0 : c5980000
    Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
    Control: c000717f Table: c0004000 DAC: 00000017
    Process swapper (pid: 1, stack limit = 0xc581a270)
    [] (__dma_alloc+0x11c/0x2d0)
    [] (dma_alloc_writecombine+0x1c/0x24)
    [] (ep93xx_pcm_preallocate_dma_buffer+0x44/0x60)
    [] (ep93xx_pcm_new+0x5c/0x88)
    [] (snd_soc_instantiate_cards+0x8a8/0xbc0)
    [] (soc_probe+0xfc/0x134)
    [] (platform_drv_probe+0x18/0x1c)
    [] (driver_probe_device+0xb0/0x16c)
    [] (bus_for_each_drv+0x48/0x84)
    [] (device_attach+0x50/0x68)
    [] (bus_probe_device+0x24/0x44)
    [] (device_add+0x2fc/0x44c)
    [] (platform_device_add+0x104/0x15c)
    [] (simone_init+0x60/0x94)
    [] (do_one_initcall+0xd0/0x1a4)

    __dma_alloc() calls (inlined) __dma_alloc_buffer() which ends up
    calling dmac_flush_range(). Now since the entries in the
    arm920_cache_fns are shifted by one, we jump into address 0xee070f38
    which is actually next instruction after the arm920_cache_fns
    structure.

    So implement flush_icache_all() for the rest of the supported CPUs
    using a generic 'invalidate I cache' instruction.

    Signed-off-by: Mika Westerberg
    Signed-off-by: Russell King

    Mika Westerberg
     

08 Oct, 2010

1 commit

27 Jul, 2010

1 commit

  • 9ca03a21e   ARM: Factor out common code from cpu_proc_fin() ... Browse Code »

    All implementations of cpu_proc_fin() start by disabling interrupts
    and then flush caches. Rather than have every processors proc_fin()
    implementation do this, move it out into generic code - and move the
    cache flush past setup_mm_for_reboot() (so it can benefit from having
    caches still enabled.)

    This allows cpu_proc_fin() to become independent of the L1/L2 cache
    types, and eventually move the L2 cache flushing into the L2 support
    code.

    Signed-off-by: Russell King

    Russell King
     

15 Feb, 2010

2 commits

14 Dec, 2009

1 commit

03 Oct, 2009

1 commit

  • 4fb284743   ARM: 5727/1: Pass IFSR register to do_PrefetchAbort() ... Browse Code »

    Instruction fault status register, IFSR, was introduced on ARMv6 to
    provide status information about the last insturction fault. It
    needed for proper prefetch abort handling.

    Now we have three prefetch abort model:

    * legacy - for CPUs before ARMv6. They doesn't provide neither
    IFSR nor IFAR. We simulate IFSR with section translation fault
    status for them to generalize code;
    * ARMv6 - provides IFSR, but not IFAR;
    * ARMv7 - provides both IFSR and IFAR.

    Signed-off-by: Kirill A. Shutemov
    Signed-off-by: Russell King

    Kirill A. Shutemov
     

01 Oct, 2008

2 commits

24 Apr, 2008

1 commit

  • 4a1fd556c   [ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84f ... Browse Code »

    The proc-*.S files have the _prefetch_abort pointer placed at the end
    of the processor structure but the cpu-multi32.h defines it in the
    second position. The patch also fixes the support for XSC3 and the
    MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi).

    Signed-off-by: Catalin Marinas
    Signed-off-by: Russell King

    Catalin Marinas
     

19 Apr, 2008

1 commit

  • 48d7927bd   Add a prefetch abort handler ... Browse Code »

    This patch adds a prefetch abort handler similar to the data abort one
    and renames the latter for consistency. Initial implementation by Paul
    Brook with some renaming by Catalin Marinas.

    Signed-off-by: Paul Brook
    Signed-off-by: Catalin Marinas

    Paul Brook
     

13 Dec, 2006

1 commit

  • ad1ae2fe7   [ARM] Unuse another Linux PTE bit ... Browse Code »

    L_PTE_ASID is not really required to be stored in every PTE, since we
    can identify it via the address passed to set_pte_at(). So, create
    set_pte_ext() which takes the address of the PTE to set, the Linux
    PTE value, and the additional CPU PTE bits which aren't encoded in
    the Linux PTE value.

    Signed-off-by: Russell King

    Russell King
     

30 Nov, 2006

1 commit

03 Jul, 2006

2 commits

  • 00eb0f6b6   [ARM] More missing proc-macros.S includes ... Browse Code »

    Signed-off-by: Russell King

    Russell King
     
  • a8c4c20df   Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm ... Browse Code »

    * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
    [ARM] 3541/2: workaround for PXA27x erratum E7
    [ARM] nommu: provide a way for correct control register value selection
    [ARM] 3705/1: add supersection support to ioremap()
    [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
    [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
    [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
    [ARM] 3703/1: Add help description for ARCH_EP80219
    [ARM] 3678/1: MMC: Make OMAP MMC work
    [ARM] 3677/1: OMAP: Update H2 defconfig
    [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
    [ARM] Add section support to ioremap
    [ARM] Fix sa11x0 SDRAM selection
    [ARM] Set bit 4 on section mappings correctly depending on CPU
    [ARM] 3666/1: TRIZEPS4 [1/5] core
    ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
    ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
    ARM: OMAP: Update dmtimers
    ARM: OMAP: Make clock variables static
    ARM: OMAP: Fix GPMC compilation when DEBUG is defined
    ARM: OMAP: Mux updates for external DMA and GPIO
    ...

    Linus Torvalds
     

02 Jul, 2006

1 commit

01 Jul, 2006

1 commit

30 Jun, 2006

1 commit

  • 8799ee9f4   [ARM] Set bit 4 on section mappings correctly depending on CPU ... Browse Code »

    On some CPUs, bit 4 of section mappings means "update the
    cache when written to". On others, this bit is required to
    be one, and others it's required to be zero. Finally, on
    ARMv6 and above, setting it turns on "no execute" and prevents
    speculative prefetches.

    With all these combinations, no one value fits all CPUs, so we
    have to pick a value depending on the CPU type, and the area
    we're mapping.

    Signed-off-by: Russell King

    Russell King
     

29 Jun, 2006

2 commits

  • 22b190861   [ARM] nommu: provide a way for correct control register value selection ... Browse Code »

    Most MMU-based CPUs have a restriction on the setting of the data cache
    enable and mmu enable bits in the control register, whereby if the data
    cache is enabled, the MMU must also be enabled. Enabling the data
    cache without the MMU is an invalid combination.

    However, there are CPUs where the data cache can be enabled without the
    MMU.

    In order to allow these CPUs to take advantage of that, provide a
    method whereby each proc-*.S file defines the control regsiter value
    for use with nommu (with the MMU disabled.) Later on, when we add
    support for enabling the MMU on these devices, we can adjust the
    "crval" macro to also enable the data cache for nommu.

    Signed-off-by: Russell King

    Russell King
     
  • d090dddab   [ARM] nommu: Initial uCLinux support for MMU-based CPUs ... Browse Code »

    In noMMU mode, various of functions which are defined in mm/proc-*.S
    is not valid or needed to be avoided. i.g. switch_mm is not needed,
    just returns and this makes the I & D caches are valid which shows
    great improvement of performance including task switching and IPC.

    Signed-off-by: Hyok S. Choi
    Signed-off-by: Russell King

    Hyok S. Choi
     

26 Mar, 2006

1 commit

22 Mar, 2006

2 commits

20 Sep, 2005

1 commit

10 Sep, 2005

1 commit

01 Jul, 2005

2 commits

17 Apr, 2005

1 commit

  • 1da177e4c   Linux-2.6.12-rc2 ... Browse Code »

    Initial git repository build. I'm not bothering with the full history,
    even though we have it. We can create a separate "historical" git
    archive of that later if we want to, and in the meantime it's about
    3.2GB when imported into git - space that would just make the early
    git days unnecessarily complicated, when we don't have a lot of good
    infrastructure for it.

    Let it rip!

    Linus Torvalds