Eric Lee / smarc-fsl-linux-kernel

06 Dec, 2011

1 commit

23 Jul, 2011

1 commit

07 Jul, 2011

1 commit

02 Jul, 2011

6 commits

23 Feb, 2011

1 commit

  • f6b0fa02e   ARM: pm: add generic CPU suspend/resume support ... Browse Code »

    This adds core support for saving and restoring CPU coprocessor
    registers for suspend/resume support. This contains support for suspend
    with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.
    Tested on Assabet and Tegra 2.

    Tested-by: Colin Cross
    Tested-by: Kukjin Kim
    Signed-off-by: Russell King

    Russell King
     

08 Oct, 2010

1 commit

27 Jul, 2010

1 commit

  • 9ca03a21e   ARM: Factor out common code from cpu_proc_fin() ... Browse Code »

    All implementations of cpu_proc_fin() start by disabling interrupts
    and then flush caches. Rather than have every processors proc_fin()
    implementation do this, move it out into generic code - and move the
    cache flush past setup_mm_for_reboot() (so it can benefit from having
    caches still enabled.)

    This allows cpu_proc_fin() to become independent of the L1/L2 cache
    types, and eventually move the L2 cache flushing into the L2 support
    code.

    Signed-off-by: Russell King

    Russell King
     

03 Feb, 2010

1 commit

03 Oct, 2009

1 commit

  • 4fb284743   ARM: 5727/1: Pass IFSR register to do_PrefetchAbort() ... Browse Code »

    Instruction fault status register, IFSR, was introduced on ARMv6 to
    provide status information about the last insturction fault. It
    needed for proper prefetch abort handling.

    Now we have three prefetch abort model:

    * legacy - for CPUs before ARMv6. They doesn't provide neither
    IFSR nor IFAR. We simulate IFSR with section translation fault
    status for them to generalize code;
    * ARMv6 - provides IFSR, but not IFAR;
    * ARMv7 - provides both IFSR and IFAR.

    Signed-off-by: Kirill A. Shutemov
    Signed-off-by: Russell King

    Kirill A. Shutemov
     

01 Oct, 2008

2 commits

24 Apr, 2008

1 commit

  • 4a1fd556c   [ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84f ... Browse Code »

    The proc-*.S files have the _prefetch_abort pointer placed at the end
    of the processor structure but the cpu-multi32.h defines it in the
    second position. The patch also fixes the support for XSC3 and the
    MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi).

    Signed-off-by: Catalin Marinas
    Signed-off-by: Russell King

    Catalin Marinas
     

19 Apr, 2008

1 commit

  • 48d7927bd   Add a prefetch abort handler ... Browse Code »

    This patch adds a prefetch abort handler similar to the data abort one
    and renames the latter for consistency. Initial implementation by Paul
    Brook with some renaming by Catalin Marinas.

    Signed-off-by: Paul Brook
    Signed-off-by: Catalin Marinas

    Paul Brook
     

13 Dec, 2006

1 commit

  • ad1ae2fe7   [ARM] Unuse another Linux PTE bit ... Browse Code »

    L_PTE_ASID is not really required to be stored in every PTE, since we
    can identify it via the address passed to set_pte_at(). So, create
    set_pte_ext() which takes the address of the PTE to set, the Linux
    PTE value, and the additional CPU PTE bits which aren't encoded in
    the Linux PTE value.

    Signed-off-by: Russell King

    Russell King
     

30 Nov, 2006

1 commit

30 Jun, 2006

1 commit

  • 8799ee9f4   [ARM] Set bit 4 on section mappings correctly depending on CPU ... Browse Code »

    On some CPUs, bit 4 of section mappings means "update the
    cache when written to". On others, this bit is required to
    be one, and others it's required to be zero. Finally, on
    ARMv6 and above, setting it turns on "no execute" and prevents
    speculative prefetches.

    With all these combinations, no one value fits all CPUs, so we
    have to pick a value depending on the CPU type, and the area
    we're mapping.

    Signed-off-by: Russell King

    Russell King
     

29 Jun, 2006

1 commit

  • d090dddab   [ARM] nommu: Initial uCLinux support for MMU-based CPUs ... Browse Code »

    In noMMU mode, various of functions which are defined in mm/proc-*.S
    is not valid or needed to be avoided. i.g. switch_mm is not needed,
    just returns and this makes the I & D caches are valid which shows
    great improvement of performance including task switching and IPC.

    Signed-off-by: Hyok S. Choi
    Signed-off-by: Russell King

    Hyok S. Choi
     

22 Mar, 2006

1 commit

20 Sep, 2005

1 commit

10 Sep, 2005

1 commit

04 Sep, 2005

1 commit

  • ca6ca91d8   [ARM] 2875/1: Data Abort fixes ... Browse Code »

    Patch from Timothy Baldwin

    All data aborts are treated as read accesses. The existing code updates the wrong bit of r1, also the comments are wrong in that the sense of the L bit is inverted.

    Signed-off-by: Timothy E. Baldwin
    Signed-off-by: Russell King

    Timothy Baldwin
     

17 Apr, 2005

1 commit

  • 1da177e4c   Linux-2.6.12-rc2 ... Browse Code »

    Initial git repository build. I'm not bothering with the full history,
    even though we have it. We can create a separate "historical" git
    archive of that later if we want to, and in the meantime it's about
    3.2GB when imported into git - space that would just make the early
    git days unnecessarily complicated, when we don't have a lot of good
    infrastructure for it.

    Let it rip!

    Linus Torvalds