Eric Lee / smarc-fsl-linux-kernel

06 Dec, 2011

1 commit

07 Jul, 2011

1 commit

23 Feb, 2011

1 commit

  • f6b0fa02e   ARM: pm: add generic CPU suspend/resume support ... Browse Code »

    This adds core support for saving and restoring CPU coprocessor
    registers for suspend/resume support. This contains support for suspend
    with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.
    Tested on Assabet and Tegra 2.

    Tested-by: Colin Cross
    Tested-by: Kukjin Kim
    Signed-off-by: Russell King

    Russell King
     

08 Oct, 2010

1 commit

27 Jul, 2010

1 commit

  • 9ca03a21e   ARM: Factor out common code from cpu_proc_fin() ... Browse Code »

    All implementations of cpu_proc_fin() start by disabling interrupts
    and then flush caches. Rather than have every processors proc_fin()
    implementation do this, move it out into generic code - and move the
    cache flush past setup_mm_for_reboot() (so it can benefit from having
    caches still enabled.)

    This allows cpu_proc_fin() to become independent of the L1/L2 cache
    types, and eventually move the L2 cache flushing into the L2 support
    code.

    Signed-off-by: Russell King

    Russell King
     

15 Feb, 2010

2 commits

14 Dec, 2009

1 commit

03 Oct, 2009

1 commit

  • 4fb284743   ARM: 5727/1: Pass IFSR register to do_PrefetchAbort() ... Browse Code »

    Instruction fault status register, IFSR, was introduced on ARMv6 to
    provide status information about the last insturction fault. It
    needed for proper prefetch abort handling.

    Now we have three prefetch abort model:

    * legacy - for CPUs before ARMv6. They doesn't provide neither
    IFSR nor IFAR. We simulate IFSR with section translation fault
    status for them to generalize code;
    * ARMv6 - provides IFSR, but not IFAR;
    * ARMv7 - provides both IFSR and IFAR.

    Signed-off-by: Kirill A. Shutemov
    Signed-off-by: Russell King

    Kirill A. Shutemov
     

23 Mar, 2009

1 commit

  • 49cbe7863   [ARM] pxa: add base support for Marvell's PXA168 processor line ... Browse Code »

    """The Marvell® PXA168 processor is the first in a family of application
    processors targeted at mass market opportunities in computing and consumer
    devices. It balances high computing and multimedia performance with low
    power consumption to support extended battery life, and includes a wealth
    of integrated peripherals to reduce overall BOM cost .... """

    See http://www.marvell.com/featured/pxa168.jsp for more information.

    1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core,
    there are many enhancements like instructions for flushing the
    whole D-cache, and so on

    2. Clock reuses Russell's common clkdev, and added the basic support
    for UART1/2.

    3. Devices are a bit different from the 'mach-pxa' way, the platform
    devices are now dynamically allocated only when necessary (i.e.
    when pxa_register_device() is called). Description for each device
    are stored in an array of 'struct pxa_device_desc'. Now that:

    a. this array of device description is marked with __initdata and
    can be freed up system is fully up

    b. which means board code has to add all needed devices early in
    his initializing function

    c. platform specific data can now be marked as __initdata since
    they are allocated and copied by platform_device_add_data()

    4. only the basic UART1/2/3 are added, more devices will come later.

    Signed-off-by: Jason Chagas
    Signed-off-by: Eric Miao

    Eric Miao