10 Jan, 2011
1 commit
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The SMP code needs "asmlinkage" which linkage.h provides.
Signed-off-by: Mike Frysinger
11 Aug, 2010
1 commit
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Now each architecture has the own dma_get_cache_alignment implementation.
dma_get_cache_alignment returns the minimum DMA alignment. Architectures
define it as ARCH_KMALLOC_MINALIGN (it's used to make sure that malloc'ed
buffer is DMA-safe; the buffer doesn't share a cache with the others). So
we can unify dma_get_cache_alignment implementations.This patch:
dma_get_cache_alignment() needs to know if an architecture defines
ARCH_KMALLOC_MINALIGN or not (needs to know if architecture has DMA
alignment restriction). However, slab.h define ARCH_KMALLOC_MINALIGN if
architectures doesn't define it.Let's rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGN.
ARCH_KMALLOC_MINALIGN is used only in the internals of slab/slob/slub
(except for crypto).Signed-off-by: FUJITA Tomonori
Cc:
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
23 May, 2010
1 commit
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Architectures that handle DMA-non-coherent memory need to set
ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is DMA-safe:
the buffer doesn't share a cache with the others.Signed-off-by: FUJITA Tomonori
Acked-by: Pekka Enberg
Signed-off-by: Mike Frysinger
07 Oct, 2009
2 commits
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Looks like the big Kconfig cache split/rename missed one spot in the SMP
cache lock headers.Signed-off-by: Graf Yang
Signed-off-by: Mike Frysinger -
Bill Gatliff & David Brownell pointed out we were missing some
copyrights, and licensing terms in some of the files in
./arch/blackfin, so this fixes things, and cleans them up.It also removes:
- verbose GPL text(refer to the top level ./COPYING file)
- file names (you are looking at the file)
- bug url (it's in the ./MAINTAINERS file)
- "or later" on GPL-2, when we did not have that rightIt also allows some Blackfin-specific assembly files to be under a BSD
like license (for people to use them outside of Linux).Signed-off-by: Robin Getz
Signed-off-by: Mike Frysinger
23 Jun, 2009
1 commit
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The current cache options don't really represent the hardware features.
They end up setting different aspects of the hardware so that the end
result is to turn on/off the cache. Unfortunately, when we hit cache
problems with the hardware, it's difficult to test different settings to
root cause the problem. The current settings also don't cleanly allow for
different caching behaviors with different regions of memory.So split the configure options such that they properly reflect the settings
that are applied to the hardware.Signed-off-by: Jie Zhang
Signed-off-by: Mike Frysinger
13 Jun, 2009
1 commit
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The KGDB code uses this when switching processors to make sure the icache
is in a valid state.Signed-off-by: Sonic Zhang
Signed-off-by: Mike Frysinger
07 Jan, 2009
1 commit
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Blackfin dual core BF561 processor can support SMP like features.
https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-likeIn this patch, we provide SMP extend to Blackfin header files
and machine common codeSigned-off-by: Graf Yang
Signed-off-by: Bryan Wu
27 Aug, 2008
1 commit
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Signed-off-by: Bryan Wu