09 Jan, 2012

1 commit

  • Recent memblock related commits require the following C6X changes:

    * commit 24aa07882b672fff2da2f5c955759f0bd13d32d5
    asm/memblock.h no longer required

    * commit 1440c4e2c918532f39131c3330fe2226e16be7b6
    memblock_analyze() no longer needed to update total size

    * commit fe091c208a40299fba40e62292a610fb91e44b4e
    memblock_init() no longer needed

    Signed-off-by: Mark Salter

    Mark Salter
     

07 Oct, 2011

16 commits

  • All SoCs provide an area of device configuration registers called the DSCR. The
    location of specific registers as well as their use varies considerably from
    implementation to implementation. Rather than having to rely on additional
    SoC-specific DSCR code for each new supported SoC, this code generalize things
    as much as possible using device tree properties. Initialization must take
    place early on (setup_arch time) in case the event timer device needs to be
    enable via the DSCR.

    Signed-off-by: Mark Salter
    Signed-off-by: Aurelien Jacquiot
    Acked-by: Arnd Bergmann

    Mark Salter
     
  • This patch provides a soc_ops struct which provides hooks for SoC functionality
    which doesn't fit well into other places.

    Signed-off-by: Mark Salter
    Signed-off-by: Aurelien Jacquiot
    Acked-by: Arnd Bergmann

    Mark Salter
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Acked-by: Arnd Bergmann

    Aurelien Jacquiot
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Acked-by: Arnd Bergmann

    Aurelien Jacquiot
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Acked-by: Arnd Bergmann

    Aurelien Jacquiot
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Acked-by: Arnd Bergmann

    Aurelien Jacquiot
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Acked-by: Arnd Bergmann

    Aurelien Jacquiot
     
  • The C6X SoCs contain several PLL controllers each with up to 16 clock outputs
    feeding into the cores or peripheral clock domains. The hardware is very similar
    to arm/mach-davinci clocks. This is still a work in progress which needs to be
    updated once device tree clock binding changes shake out.

    Signed-off-by: Mark Salter
    Signed-off-by: Aurelien Jacquiot
    Acked-by: Arnd Bergmann

    Mark Salter
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Acked-by: Arnd Bergmann

    Aurelien Jacquiot
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Acked-by: Arnd Bergmann
    [msalter@redhat.com: add include of linux/module.h to sys_c6x.c]
    Signed-off-by: Mark Salter

    Aurelien Jacquiot
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Reviewed-by: Thomas Gleixner
    Acked-by: Arnd Bergmann

    Aurelien Jacquiot
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Reviewed-by: Thomas Gleixner
    Acked-by: Arnd Bergmann

    Aurelien Jacquiot
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Acked-by: Arnd Bergmann

    Aurelien Jacquiot
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Acked-by: Arnd Bergmann

    Aurelien Jacquiot
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    The C6X architecture currently lacks an MMU so memory management is relatively
    simple. There is no bus snooping between L2 and main memory but coherent DMA
    memory is supported by making regions of main memory uncached. If such a region
    is desired, it can be specified on the commandline with a "memdma=" argument.

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Acked-by: Arnd Bergmann

    Aurelien Jacquiot
     
  • Original port to early 2.6 kernel using TI COFF toolchain.
    Brought up to date by Mark Salter

    Signed-off-by: Aurelien Jacquiot
    Signed-off-by: Mark Salter
    Acked-by: Arnd Bergmann

    Aurelien Jacquiot