08 Dec, 2011
1 commit
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This patch refactors MIPS branch emulation code so as to allow skipping
delay slot instruction in case of branch likely instructions when branch is
not taken. This is useful for keeping the code common for use cases like
kprobes where one would like to handle the branch instructions keeping the
delay slot instuction also in picture for branch likely instructions. Also
allow emulation when instruction to be decoded is not at pt_regs->cp0_epc
as in case of kprobes where pt_regs->cp0_epc points to the breakpoint
instruction.The patch also exports the function for modules.
Signed-off-by: Maneesh Soni
Signed-off-by: Victor Kamensky
Cc: David Daney
Cc: ananth@in.ibm.com
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2913/
Signed-off-by: Ralf Baechle
01 Jul, 2011
1 commit
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The nmi parameter indicated if we could do wakeups from the current
context, if not, we would set some state and self-IPI and let the
resulting interrupt do the wakeup.For the various event classes:
- hardware: nmi=0; PMI is in fact an NMI or we run irq_work_run from
the PMI-tail (ARM etc.)
- tracepoint: nmi=0; since tracepoint could be from NMI context.
- software: nmi=[0,1]; some, like the schedule thing cannot
perform wakeups, and hence need 0.As one can see, there is very little nmi=1 usage, and the down-side of
not using it is that on some platforms some software events can have a
jiffy delay in wakeup (when arch_irq_work_raise isn't implemented).The up-side however is that we can remove the nmi parameter and save a
bunch of conditionals in fast paths.Signed-off-by: Peter Zijlstra
Cc: Michael Cree
Cc: Will Deacon
Cc: Deng-Cheng Zhu
Cc: Anton Blanchard
Cc: Eric B Munson
Cc: Heiko Carstens
Cc: Paul Mundt
Cc: David S. Miller
Cc: Frederic Weisbecker
Cc: Jason Wessel
Cc: Don Zickus
Link: http://lkml.kernel.org/n/tip-agjev8eu666tvknpb3iaj0fg@git.kernel.org
Signed-off-by: Ingo Molnar
17 Dec, 2010
1 commit
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We were unconditionally sending SIGBUS with an empty siginfo on FP
emulator faults. This differs from what happens when real floating
point hardware would get a fault.For most faults we need to send SIGSEGV with the faulting address
filled in in the struct siginfo.Reported-by: Camm Maguire
Signed-off-by: David Daney
To: linux-mips@linux-mips.org
Cc: Camm Maguire
Patchwork: https://patchwork.linux-mips.org/patch/1727/
Signed-off-by: Ralf Baechle
30 Oct, 2010
1 commit
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Software events are required as part of the measurable stuff by the
Linux performance counter subsystem. Here is the list of events added by
this patch:
PERF_COUNT_SW_PAGE_FAULTS
PERF_COUNT_SW_PAGE_FAULTS_MIN
PERF_COUNT_SW_PAGE_FAULTS_MAJ
PERF_COUNT_SW_ALIGNMENT_FAULTS
PERF_COUNT_SW_EMULATION_FAULTSSigned-off-by: Deng-Cheng Zhu
To: linux-mips@linux-mips.org
Cc: a.p.zijlstra@chello.nl
Cc: paulus@samba.org
Cc: mingo@elte.hu
Cc: acme@redhat.com
Cc: jamie.iles@picochip.com
Acked-by: David Daney
Reviewed-by: Matt Fleming
Patchwork: https://patchwork.linux-mips.org/patch/1686/
Signed-off-by: Ralf Baechle
18 Oct, 2010
1 commit
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The patch below updates broken web addresses in the arch directory.
Signed-off-by: Justin P. Mattock
Signed-off-by: Maciej W. Rozycki
Cc: Finn Thain
Cc: Randy Dunlap
Reviewed-by: Finn Thain
Signed-off-by: Jiri Kosina
22 May, 2010
1 commit
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Replaces references to the magic number 0x3 with constants and macros
indicating the real purpose of those bits. They are the rounding mode
bits of the FCSR register.Signed-off-by: Shane McDonald
To: anemo@mba.ocn.ne.jp
To: kevink@paralogos.com
To: linux-mips@linux-mips.org
To: sshtylyov@mvista.com
Patchwork: http://patchwork.linux-mips.org/patch/1206/
Signed-off-by: Ralf Baechle
16 May, 2010
1 commit
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In the FPU emulator code of the MIPS, the Cause bits of the FCSR register
are not currently writeable by the ctc1 instruction. In odd corner cases,
this can cause problems. For example, a case existed where a divide-by-zero
exception was generated by the FPU, and the signal handler attempted to
restore the FPU registers to their state before the exception occurred. In
this particular setup, writing the old value to the FCSR register would
cause another divide-by-zero exception to occur immediately. The solution
is to change the ctc1 instruction emulator code to allow the Cause bits of
the FCSR register to be writeable. This is the behaviour of the hardware
that the code is emulating.This problem was found by Shane McDonald, but the credit for the fix goes
to Kevin Kissell. In Kevin's words:I submit that the bug is indeed in that ctc_op: case of the emulator. The
Cause bits (17:12) are supposed to be writable by that instruction, but the
CTC1 emulation won't let them be updated by the instruction. I think that
actually if you just completely removed lines 387-388 [...] things would
work a good deal better. At least, it would be a more accurate emulation of
the architecturally defined FPU. If I wanted to be really, really pedantic
(which I sometimes do), I'd also protect the reserved bits that aren't
necessarily writable.Signed-off-by: Shane McDonald
To: anemo@mba.ocn.ne.jp
To: kevink@paralogos.com
To: sshtylyov@mvista.com
Patchwork: http://patchwork.linux-mips.org/patch/1205/
Signed-off-by: Ralf Baechle---
17 Dec, 2009
1 commit
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On SMP systems, the collection of statistics can cause cache line
bouncing in the lines associated with the counters. Also there are
races incrementing the counters on multiple CPUs.To fix both problems, we collect the statistics in per-CPU variables,
and add them up in the debugfs read operation.As a test I ran the LTP float_bessel test on a 12 CPU Octeon system.
Without CONFIG_DEBUG_FS : 2602 seconds.
With CONFIG_DEBUG_FS: 2640 seconds.
With non-cpu-local atomic statistics: 14569 seconds.Signed-off-by: David Daney
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle
14 Nov, 2009
1 commit
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Running a 64-bit kernel on a 64-bit CPU without an FPU would cause the
emulator to run in 32-bit mode. The c0_Status.FR bit is wired to zero
on systems without an FPU, so using that bit to decide how the emulator
behaves doesn't allow for proper emulation on 64-bit FPU-less
processors.Instead, we need to select the emulator mode based on the user-space
ABI. Since the thread flag TIF_32BIT_REGS is used to set c0_Status.FR,
we can just use it to decide if the emulator should be in 32-bit or
64-bit mode.Signed-off-by: David Daney
Signed-off-by: Ralf Baechle
30 Oct, 2008
1 commit
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Arguably using the address error handler has always been ugly. But with
processors that handle unaligned loads and stores in hardware the
current mechanism ceases to work so switch it to a BREAK instruction and
allocate break code 514 to the FPU emulator.Yoichi Yuasa provided a build fix for CONFIG_BUG=n.
Signed-off-by: Ralf Baechle
Signed-off-by: Yoichi Yuasa
28 Oct, 2008
1 commit
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debugfs_create_*() returns NULL on error. Make its caller debugfs_fpuemu
return -ENODEV on error.Signed-off-by: Zhao Lei
Signed-off-by: Ralf Baechle
12 Oct, 2007
2 commits
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Signed-off-by: Ralf Baechle
-
Signed-off-by: Ralf Baechle
14 Jul, 2007
1 commit
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Declaring emulpc and contpc as "unsigned long" can get rid of some casts.
This also get rid of some sparse warnings.Signed-off-by: Atsushi Nemoto
Signed-off-by: Ralf Baechle
11 Jul, 2007
1 commit
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Export contents of struct mips_fpu_emulator_stats via debugfs.
There is no way to read these statistics for now but they (at least
the "emulated" count) might be sometimes useful for performance tuning
on FPU-less CPUs.Signed-off-by: Atsushi Nemoto
Signed-off-by: Ralf Baechle
10 Oct, 2006
1 commit
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Make sure cpu_has_fpu (which uses smp_processor_id()) is used only in
atomic context.Signed-off-by: Atsushi Nemoto
Signed-off-by: Ralf Baechle
20 Jun, 2006
1 commit
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The struct mips_fpu_soft_struct and mips_fpu_hard_struct are
completely same now and the kernel fpu emulator assumes that. This
patch unifies them to mips_fpu_struct and get rid of mips_fpu_union.Signed-off-by: Atsushi Nemoto
Signed-off-by: Ralf Baechle
30 Oct, 2005
7 commits
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by emulation of a full FPU.
Signed-off-by: Ralf Baechle
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Signed-off-by: Ralf Baechle
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First argument of fpu_emulator_cop1Handler() was unused.
Signed-off-by: Ralf Baechle
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processors.
Signed-off-by: Ralf Baechle
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mips_fpu_emulator_stats cleanup that unnecessary nesting of structs.
Signed-off-by: Ralf Baechle
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Signed-off-by: Ralf Baechle
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VA_TO_REG. Who ever wrote this apparently did enjoy the C Puzzle Book.
ISBN 0201604612, a little old but still fun reading for the next
blackout ;)Signed-off-by: Ralf Baechle
05 Sep, 2005
1 commit
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This patch has fixed the following warnings.
arch/mips/kernel/genex.S:250:5: warning: "CONFIG_64BIT" is not defined
arch/mips/math-emu/cp1emu.c:1128:5: warning: "__mips64" is not defined
arch/mips/math-emu/cp1emu.c:1206:5: warning: "__mips64" is not defined
arch/mips/math-emu/cp1emu.c:1270:5: warning: "__mips64" is not defined
arch/mips/math-emu/cp1emu.c:323:5: warning: "__mips64" is not defined
arch/mips/math-emu/cp1emu.c:808:5: warning: "__mips64" is not defined
arch/mips/math-emu/cp1emu.c:953:5: warning: "__mips64" is not defined
arch/mips/mm/tlbex.c:519:5: warning: "CONFIG_64BIT" is not defined
include/asm/reg.h:73:5: warning: "CONFIG_64BIT" is not definedSigned-off-by: Yoichi Yuasa
Cc: Ralf Baechle
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
17 Apr, 2005
1 commit
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Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.Let it rip!
