27 Jul, 2011
1 commit
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This allows us to move duplicated code in
(atomic_inc_not_zero() for now) toSigned-off-by: Arun Sharma
Reviewed-by: Eric Dumazet
Cc: Ingo Molnar
Cc: David Miller
Cc: Eric Dumazet
Acked-by: Mike Frysinger
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
08 Jun, 2011
1 commit
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One of the kernel debugger cacheflush variants escaped proper testing. Two of
the labels are wrong, being derived from the code that was copied to construct
the variant.The first label results in the following assembler message:
AS arch/mn10300/mm/cache-dbg-flush-by-reg.o
arch/mn10300/mm/cache-dbg-flush-by-reg.S: Assembler messages:
arch/mn10300/mm/cache-dbg-flush-by-reg.S:123: Error: symbol `debugger_local_cache_flushinv_no_dcache' is already definedAnd the second label results in the following linker message:
arch/mn10300/mm/built-in.o:(.text+0x1d39): undefined reference to `mn10300_local_icache_inv_range_reg_end'
arch/mn10300/mm/built-in.o:(.text+0x1d39): relocation truncated to fit: R_MN10300_PCREL16 against undefined symbol `mn10300_local_icache_inv_range_reg_end'To test this file the following configuration pieces must be set:
CONFIG_AM34=y
CONFIG_MN10300_CACHE_WBACK=y
CONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_REG=y
CONFIG_MN10300_CACHE_MANAGE_BY_REG=y
CONFIG_AM34_HAS_CACHE_SNOOP=nSigned-off-by: David Howells
Signed-off-by: Linus Torvalds
25 May, 2011
2 commits
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Adapt to the new API.
We plan to remove old cpumask APIs later. Thus this patch converts them
into the new one.Signed-off-by: KOSAKI Motohiro
Cc: David Howells
Cc: Koichi Yasutake
Cc: Hugh Dickins
Cc: Chris Metcalf
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
Fold all the mmu_gather rework patches into one for submission
Signed-off-by: Peter Zijlstra
Reported-by: Hugh Dickins
Cc: Benjamin Herrenschmidt
Cc: David Miller
Cc: Martin Schwidefsky
Cc: Russell King
Cc: Paul Mundt
Cc: Jeff Dike
Cc: Richard Weinberger
Cc: Tony Luck
Cc: KAMEZAWA Hiroyuki
Cc: Mel Gorman
Cc: KOSAKI Motohiro
Cc: Nick Piggin
Cc: Namhyung Kim
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
19 Mar, 2011
3 commits
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Create generic kernel debugger hooks in the MN10300 arch and make gdbstub use
them. This is a preparation for KGDB support.Signed-off-by: David Howells
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Create general kernel debugger cache flushing for MN10300 and get rid of the
old stuff that gdbstub was using.Signed-off-by: David Howells
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The icache invalidate functions should disable the icache on AM33 and wait for
it to quiesce before attempting to invalidate it, and should then wait for it
to quiesce again before reenabling it, but on AM34 they should invalidate
directly. The same goes for the dcache invalidation, but this isn't used much.Whilst we're at it, this can be wrapped in assembler macros to remove duplicate
code.The AM33 manual states that:
An operation that invalidates the cache, switches the writing mode, or
changes the way mode must be performed after disabling the cache,
checking the busy bit, and confirming that the cache is not in
operation.for the dcache [sec 2.8.3.2.1]. This is not stated so for the icache [sec
2.8.3.1.1] but the example code there suggests that it is.Whilst the AM34 manual states that the cache must be disabled for both the
icache [sec 1.8.3.2.1] and the dcache [sec 1.8.3.2.1], the Panasonic hardware
engineers say the manual is wrong and that disabling the caches for
invalidation is wrong.Furthermore, they say that disabling the caches on the AM34 whilst running an
SMP kernel can lead to incoherency between the various CPU caches and should
thus be avoided.Signed-off-by: David Howells
14 Mar, 2011
1 commit
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The invalidate-only versions of flush_icache_*range() are trying sending the
SMP_ICACHE_INV_FLUSH_RANGE IPI command in SMP kernels when they should be
sending SMP_ICACHE_INV_RANGE as the former does not exist.Signed-off-by: David Howells
28 Oct, 2010
17 commits
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The AM34 processor has an atomic operation that's the equivalent of LL/SC on
other architectures. However, rather than being done through a pair of
instructions, it's driven by writing to a pair of memory-mapped CPU control
registers.One set of these registers (AARU/ADRU/ASRU) is available for use by userspace,
but for userspace to access them a PTE must be set up to cover the region.
This is done by dedicating the first vmalloc region page to this purpose,
setting the permissions on its PTE such that userspace can access the page.glibc is hardcoded to expect the registers to be there.
The way atomic ops are done through these registers is straightforward:
(1) Write the address of the word you wish to access into AARU. This causes
the CPU to go and fetch that word and load it into ADRU. The status bits
are also cleared in ASRU.(2) The current data value is read from the ADRU register and modified.
(3) To alter the data in RAM, the revised data is written back to the ADRU
register, which causes the CPU to attempt to write it back.(4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch),
ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then
must be checked to confirm that the operation wasn't aborted. If any of
the watches have been set to true, the operation was aborted.Signed-off-by: Mark Salter
Signed-off-by: David Howells -
Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for
MN10300. Also implement support for the MN2WS0060 processor and the ASB2364
evaluation board which are AM34 based.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
Implement global TLB flushing for MN10300. This will be used by the AM34 which
is SMP capable.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits
are a more suitable layout.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
Make controllable the use of the PIDR register to mark TLB entries as belonging
to particular processes.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
Rename __flush_tlb*() to local_flush_tlb*() as it's more appropriate, and ready
to differentiate local from global TLB flushes when SMP is introduced.Whilst we're at it, get rid of __flush_tlb_global() and make
local_flush_tlb_page() take an mm_struct pointer rather than VMA pointer.Signed-off-by: David Howells
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An AM34 erratum requires MMUCTR read and write on entry to certain exceptions,
prior to EPSW.NMID being cleared to allow NMIs to happen.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
Implement SMP global cache flushing for MN10300. This will be used by the AM34
which is SMP capable.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
The AM34 core is able to do cache snooping, and so can skip some of the cache
flushing.Signed-off-by: David Howells
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The AM34 CPU core provides an automated way of purging the cache rather than
manually iterating over all the tags in the cache. Make it possible to use
these.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
Differentiate local cache flushing from global cache flushing so that they can
be done differently on SMP systems.Rename the cache functions from:
mn10300_[id]cache_*()
to:
mn10300_[id]_localcache_*()
and on a UP system, assign the global labels to the local labels.
Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
The functions that perform cache flushing should take addresses of unsigned
long type, not unsigned int.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
The current cache flush and invalidate routines operate by controlling the
cache tag registers. Rename the files and add config items to select them.This makes it easier to support the use of other cache flush methods instead,
such as the use of AM34's area purge registers, if available.Signed-off-by: David Howells
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Provide a MN10300_CACHE_ENABLED config option as inverted logic of
MN10300_CACHE_DISABLED to make things simpler.Signed-off-by: David Howells
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Split the cache bits out of arch/mn10300/Kconfig as they're quite complex.
Signed-off-by: David Howells
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Remove the monitor trap function and the set_jtag_stub function as they're not
really necessary.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
Signed-off-by: Stoyan Gaydarov
Signed-off-by: David Howells
02 Oct, 2010
1 commit
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flush_icache_range() is given virtual addresses to describe the region. It
deals with these by attempting to translate them through the current set of
page tables.This is fine for userspace memory and vmalloc()'d areas as they are governed by
page tables. However, since the regions above 0x80000000 aren't translated
through the page tables by the MMU, the kernel doesn't bother to set up page
tables for them (see paging_init()).This means flush_icache_range() as it stands cannot be used to flush regions of
the VM area between 0x80000000 and 0x9fffffff where the kernel resides if the
data cache is operating in WriteBack mode.To fix this, make flush_icache_range() first check for addresses in the upper
half of VM space and deal with them appropriately, before dealing with any
range in the page table mapped area.Ordinarily, this is not a problem, but it has the capacity to make kprobes and
kgdb malfunction. It should not affect gdbstub, signal frame setup or module
loading as gdb has its own flush functions, and the others take place in the
page table mapped area only.Signed-off-by: David Howells
Acked-by: Akira Takeuchi
Signed-off-by: Linus Torvalds
29 Sep, 2010
1 commit
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When caching is disabled on the MN10300 arch, the sys_cacheflush()
function is removed by conditional stuff in the makefiles, but is still
referred to by the syscall table.Provide a null version that just returns 0 when caching is disabled (or
-EINVAL if the arguments are silly).Signed-off-by: David Howells
Signed-off-by: Linus Torvalds
24 Aug, 2010
1 commit
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dev_name always dereferences its argument, so it should not be called if
the argument is NULL. The function indeed later tests the argument for
being NULL.The semantic match that finds this problem is as follows:
(http://coccinelle.lip6.fr/)//
@@
expression dev,E;
@@*dev_name(dev)
... when != dev = E
(
*dev == NULL
|
*dev != NULL
)
//Signed-off-by: Julia Lawall
Signed-off-by: David Howells
Signed-off-by: Linus Torvalds
05 Jun, 2010
1 commit
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As explained in commit 1c0fe6e3bd ("mm: invoke oom-killer from page
fault") , we want to call the architecture independent oom killer when
getting an unexplained OOM from handle_mm_fault, rather than simply
killing current.Signed-off-by: Nick Piggin
Acked-by: David Rientjes
Acked-by: David Howells
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
30 Mar, 2010
1 commit
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…it slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
21 Feb, 2010
1 commit
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On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies. We do this via make_coherent() by making the pages
uncacheable.This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
to construct a pointer to the pte again. Passing a pte_t * is much
more elegant. Maybe we might even replace the pte argument with the
pte_t?Ben Herrenschmidt would also like the pte pointer for PowerPC:
Passing the ptep in there is exactly what I want. I want that
-instead- of the PTE value, because I have issue on some ppc cases,
for I$/D$ coherency, where set_pte_at() may decide to mask out the
_PAGE_EXEC.So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.Includes a fix from Stephen Rothwell:
sparc: fix fallout from update_mmu_cache API change
Signed-off-by: Stephen Rothwell
Acked-by: Benjamin Herrenschmidt
Signed-off-by: Russell King
12 Jan, 2010
3 commits
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Access to the ASB2305's PCnet32 NIC doesn't work correctly because when
the NIC attempts to update the ring buffer flags by DMA, the change to RAM
crops up about 17uS after the interrupt line is asserted. This is almost
certainly due to a bug in the PCI bridge FPGA on that board.We can get around this by making dma_alloc_coherent() put the ring buffer
in the SRAM attached to the PCI bridge rather than in the SDRAM.Signed-off-by: David Howells
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
gcc 4.2.1 for MN10300 is more agressive than the older gcc in
reordering/moving other insns between an insn that sets flags and an insn
that uses those flags. This leads to trouble with asm statements which
are missing an explicit "cc" clobber. This patch adds the explicit "cc"
clobber to asm statements which do indeed clobber the condition flags.Signed-off-by: Mark Salter
Signed-off-by: David Howells
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
Makes it consistent with the extern declaration, used when CONFIG_HIGHMEM
is set Removes redundant casts in printout messagesSigned-off-by: Andreas Fenkart
Acked-by: Russell King
Cc: Ralf Baechle
Cc: David Howells
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: "H. Peter Anvin"
Cc: Chen Liqin
Cc: Lennox Wu
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
22 Sep, 2009
1 commit
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Commit 96177299416dbccb73b54e6b344260154a445375 ("Drop free_pages()")
modified nr_free_pages() to return 'unsigned long' instead of 'unsigned
int'. This made the casts to 'unsigned long' in most callers superfluous,
so remove them.[akpm@linux-foundation.org: coding-style fixes]
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Christoph Lameter
Acked-by: Ingo Molnar
Acked-by: Russell King
Acked-by: David S. Miller
Acked-by: Kyle McMartin
Acked-by: WANG Cong
Cc: Richard Henderson
Cc: Ivan Kokshaysky
Cc: Haavard Skinnemoen
Cc: Mikael Starvik
Cc: "Luck, Tony"
Cc: Hirokazu Takata
Cc: Ralf Baechle
Cc: David Howells
Acked-by: Benjamin Herrenschmidt
Cc: Martin Schwidefsky
Cc: Paul Mundt
Cc: Chris Zankel
Cc: Michal Simek
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
13 Jul, 2009
1 commit
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* Remove smp_lock.h from files which don't need it (including some headers!)
* Add smp_lock.h to files which do need it
* Make smp_lock.h include conditional in hardirq.h
It's needed only for one kernel_locked() usage which is under CONFIG_PREEMPTThis will make hardirq.h inclusion cheaper for every PREEMPT=n config
(which includes allmodconfig/allyesconfig, BTW)Signed-off-by: Alexey Dobriyan
Signed-off-by: Linus Torvalds
22 Jun, 2009
1 commit
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This allows the callers to now pass down the full set of FAULT_FLAG_xyz
flags to handle_mm_fault(). All callers have been (mechanically)
converted to the new calling convention, there's almost certainly room
for architectures to clean up their code and then add FAULT_FLAG_RETRY
when that support is added.Signed-off-by: Linus Torvalds
12 Jun, 2009
1 commit
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Remove the special handling for the Data TLB entry dirty bit in the TLB-miss
handler. As the code stands, all that it does is to cause us to take a second
data address exception to set the dirty bit. Instead, we can just let
pte_mkdirty() set the bit.Signed-off-by: David Howells
Signed-off-by: Linus Torvalds
13 Nov, 2008
2 commits
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Don't do misalignment handling for userspace misalignment faults: just
generate an appropriate SIGBUS instead.Signed-off-by: David Howells
Signed-off-by: Linus Torvalds -
Don't handle the misaligned loading and storing of the SP register as in C code
that's most certainly a compiler bug.Signed-off-by: David Howells
Signed-off-by: Linus Torvalds