05 Jan, 2012
1 commit
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Integrated Flash Controller supports various flashes like NOR, NAND
and other devices using NOR, NAND and GPCM Machine available on it.
IFC supports four chip selects.Signed-off-by: Dipen Dudhat
Signed-off-by: Scott Wood
Signed-off-by: Li Yang
Signed-off-by: Liu Shuo
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Kumar Gala
24 Nov, 2011
1 commit
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The Freescale PowerPC RapidIO controller consists of a RapidIO endpoint and
a RapidIO message unit(RMU). Or use RapidIO message manager(RMan) to
replace the RMU in DPAA architecture. Therefore, we should split the code
into two function modules according to the hardware architecture. Add new
struct for RMU module, and new initialization function to set up RMU
module. This policy is very conducive to adding new module like RMan, or
adding multi-ports or message units support.Signed-off-by: Lian Minghuan
Signed-off-by: Liu Gang
Acked-by: Alexandre Bounine
Signed-off-by: Kumar Gala
23 Sep, 2011
1 commit
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Move the driver to the place where it is expected to be nowadays. Also
rename its CONFIG-name to match the rest and adapt the defconfigs.
Finally, move selection of REQUIRE_GPIOLIB or WANTS_OPTIONAL_GPIOLIB to
the platforms, because this option is per-platform and not per-driver.Signed-off-by: Wolfram Sang
Cc: Anatolij Gustschin
Cc: Grant Likely
Cc: Benjamin Herrenschmidt
Acked-by: Grant Likely
Signed-off-by: Anatolij Gustschin
27 Jun, 2011
1 commit
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The Freescale ePAPR reference hypervisor provides interrupt controller
services via a hypercall interface, instead of emulating the MPIC
controller. This is called the VMPIC.The ePAPR "virtual interrupt controller" provides interrupt controller
services for external interrupts. External interrupts received by a
partition can come from two sources:- Hardware interrupts - hardware interrupts come from external
interrupt lines or on-chip I/O devices.
- Virtual interrupts - virtual interrupts are generated by the hypervisor
as part of some hypervisor service or hypervisor-created virtual device.Both types of interrupts are processed using the same programming model and
same set of hypercalls.Signed-off-by: Ashish Kalra
Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala
26 May, 2011
1 commit
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This patch adds MSI support for 440SPe, 460Ex, 460Sx and 405Ex.
Signed-off-by: Rupjyoti Sarmah
Signed-off-by: Tirumala R Marri
Acked-by: Josh Boyer
Signed-off-by: Benjamin Herrenschmidt
20 Apr, 2011
2 commits
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SCOM is a side-band configuration bus implemented on some processors.
This code provides a way for code to map and operate on devices via
SCOM, while the details of how that is implemented is left up to a
SCOM "controller" in the platform code.Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Michael Ellerman
Signed-off-by: Benjamin Herrenschmidt -
This is a significant rework of the XICS driver, too significant to
conveniently break it up into a series of smaller patches to be honest.The driver is moved to a more generic location to allow new platforms
to use it, and is broken up into separate ICP and ICS "backends". For
now we have the native and "hypervisor" ICP backends and one common
RTAS ICS backend.The driver supports one ICP backend instanciation, and many ICS ones,
in order to accomodate future platforms with multiple possibly different
interrupt "sources" mechanisms.Signed-off-by: Benjamin Herrenschmidt
24 Mar, 2011
1 commit
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1. Add an option to include RapidIO support if the PCI is available.
2. Add FSL_RIO configuration option to enable controller selection.
3. Add RapidIO support option into x86 and MIPS architectures.Signed-off-by: Alexandre Bounine
Acked-by: Kumar Gala
Cc: Matt Porter
Cc: Li Yang
Cc: Thomas Moll
Cc: Micha Nelissen
Cc: Benjamin Herrenschmidt
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
29 Nov, 2010
1 commit
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Add suspend/resume support for 4xx compatible CPUs.
See /sys/power/state for available power states configured in.Add two different idle states (idle-wait and idle-doze) controlled via sysfs.
Default is idle-wait.
cat /sys/devices/system/cpu/cpu0/idle
[wait] dozeTo save additional power, use idle-doze.
echo doze > /sys/devices/system/cpu/cpu0/idle
cat /sys/devices/system/cpu/cpu0/idle
wait [doze]Signed-off-by: Victor Gallardo
Signed-off-by: Josh Boyer
14 Oct, 2010
1 commit
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It adds cache-sram support in P1/P2 QorIQ platforms as under:
* A small abstraction over powerpc's remote heap allocator
* Exports mpc85xx_cache_sram_alloc()/free() APIs
* Supports only one contiguous SRAM window
* Drivers can do the following in Kconfig to use these APIs
"select FSL_85XX_CACHE_SRAM if MPC85xx"
* Required SRAM size and the offset where SRAM should be mapped must be
provided at kernel command line as :
cache-sram-size=
cache-sram-offset=Signed-off-by: Harninder Rai
Signed-off-by: Vivek Mahajan
Signed-off-by: Kumar Gala
13 Oct, 2010
1 commit
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Replace EXTRA_CFLAGS with ccflags-y and EXTRA_AFLAGS with asflags-y.
Signed-off-by: matt mooney
Signed-off-by: Benjamin Herrenschmidt
12 Nov, 2009
1 commit
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This patch adds suspend/resume support for MPC8540 and MPC8641D-
compatible CPUs. To reach sleep state, we just write the SLP bit
into the PM control and status register.So far we don't support Deep Sleep mode as found in newer MPC85xx
CPUs (i.e. MPC8536). It can be relatively easy implemented though,
and for it we reserve 'mem' suspend type.Signed-off-by: Anton Vorontsov
Acked-by: Scott Wood
Signed-off-by: Kumar Gala
17 Jun, 2009
1 commit
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So far, MPC512x used mpc512x_find_ips_freq() to get the bus frequency,
while MPC52xx used mpc52xx_find_ipb_freq(). Despite the different
clock names (IPS vs. IPB) the code was identical.Use common code for both processor families.
Signed-off-by: Wolfgang Denk
Signed-off-by: Grant Likely
16 Jun, 2009
1 commit
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Add the option to build the code under arch/powerpc with -Werror.
The intention is to make it harder for people to inadvertantly introduce
warnings in the arch/powerpc code. It needs to be configurable so that
if a warning is introduced, people can easily work around it while it's
being fixed.The option is a negative, ie. don't enable -Werror, so that it will be
turned on for allyes and allmodconfig builds.The default is n, in the hope that developers will build with -Werror,
that will probably lead to some build breaks, I am prepared to be flamed.It's not enabled for math-emu, which is a steaming pile of warnings.
Signed-off-by: Michael Ellerman
Signed-off-by: Benjamin Herrenschmidt
07 Jun, 2009
1 commit
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This patch adds support for the Xilinx plbv46-pci-1.03.a PCI host
bridge IPcore.Signed-off-by: Roderick Colenbrander
Signed-off-by: Grant Likely
31 Dec, 2008
1 commit
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The driver supports very simple GPIO controllers, that is, when a
controller provides just a 'data' register. Such controllers may be
found in various BCSRs (Board's FPGAs used to control board's
switches, LEDs, chip-selects, Ethernet/USB PHY power, etc).So far we support only 1-byte GPIO banks. Support for other widths may
be implemented when/if needed.p.s.
To avoid "made up" compatible entries (like compatible = "simple-gpio"),
boards must call simple_gpiochip_init() to pass the compatible string.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala
18 Oct, 2008
1 commit
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This patch adds support for the GPIO functions of PPC40x and PPC44x
SOCs.Signed-off-by: Steve Falco
Acked-by: Stefan Roese
Acked-by: Sean MacLennan
Signed-off-by: Josh Boyer
13 Oct, 2008
1 commit
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There is an old workaround in the sysdev/Makefile for dealing
with arch/ppc vs. arch/powerpc compiles. This is no longer
needed as arch/ppc is dead.Signed-off-by: Josh Boyer
Acked-by: Kumar Gala
Signed-off-by: Benjamin Herrenschmidt
23 Sep, 2008
1 commit
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Structured similar to the existing QE GPIO support.
Signed-off-by: Peter Korsgaard
Acked-by: Anton Vorontsov
Signed-off-by: Kumar Gala
20 Aug, 2008
1 commit
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There are now two almost identical implementations of an MSI bitmap
allocator, one in mpic_msi.c and the other in fsl_msi.c.Merge them together and put the result in msi_bitmap.c. Some of the
MPIC bits will remain to provide a nicer interface for the MPIC users.In the process we fix two buglets. The first is that the allocation
routines, now msi_bitmap_alloc_hwirqs(), returned an unsigned result,
even though they use -1 to indicate allocation failure. Although all
the callers were checking correctly, it is much better for the routine
to just return an int. At least until someone wants > ~2 billion MSIs.The second buglet is that the device tree reservation logic only
allowed power-of-two reservations. AFAICT that didn't effect any
existing code but it's nicer if we can reserve arbitrary irqs from MSI
use.We also add some selftests, which exposed the two buglets and now test
for them, as well as some basic sanity tests. The tests are only built
when CONFIG_DEBUG_KERNEL=y.Signed-off-by: Michael Ellerman
Signed-off-by: Paul Mackerras
04 Aug, 2008
1 commit
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Now that arch/ppc is gone and CONFIG_PPC_MERGE is always set, remove
the dead code associated with !CONFIG_PPC_MERGE from arch/powerpc
and include/asm-powerpc.Signed-off-by: Kumar Gala
Signed-off-by: Paul Mackerras
11 Jun, 2008
1 commit
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This is very trivial patch. We're transitioning to the cpm_muram_*
calls. That's it.Less trivial changes:
- BD_SC_* defines were defined in the cpm.h and qe.h, so to avoid redefines
we remove BD_SC from the qe.h and use cpm.h along with cpm_muram_*
prototypes;
- qe_muram_dump was unused and thus removed;
- added some code to the cpm_common.c to support legacy QE bindings
(data-only node name).
- For convenience, define qe_* calls to cpm_*. So drivers need not to be
changed.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala
10 Jun, 2008
1 commit
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GTM stands for General-purpose Timers Module and able to generate
timer{1,2,3,4} interrupts. These timers are used by the drivers that
need time precise interrupts (like for USB transactions scheduling for
the Freescale USB Host controller as found in some QE and CPM chips),
or these timers could be used as wakeup events from the CPU deep-sleep
mode.Things unimplemented:
1. Cascaded (32 bit) timers (1-2, 3-4).
This is straightforward to implement when needed, two timers should
be marked as "requested" and configured as appropriate.
2. Super-cascaded (64 bit) timers (1-2-3-4).
This is also straightforward to implement when needed, all timers
should be marked as "requested" and configured as appropriate.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala
03 Jun, 2008
1 commit
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This MSI driver can be used on 83xx/85xx/86xx board.
In this driver, virtual interrupt host and chip were
setup. There are 256 MSI interrupts in this host, Every 32
MSI interrupts cascaded to one IPIC/MPIC interrupt.
The chip was treated as edge sensitive and some necessary
functions were setup for this chip.Before using the MSI interrupt, PCI/PCIE device need to
ask for a MSI interrupt in the 256 MSI interrupts. A 256bit
bitmap show which MSI interrupt was used, reserve bit in
the bitmap can be used to force the device use some designate
MSI interrupt in the 256 MSI interrupts. Sometimes this is useful
for testing the all the MSI interrupts. The msi-available-ranges
property in the dts file was used for this purpose.Signed-off-by: Jason Jin
Signed-off-by: Kumar Gala
16 May, 2008
1 commit
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This adds a function to put a 6xx/7xx/7xxx/83xx family CPU into sleep
mode, and return after an interrupt has occurred. It expects to be
called with interrupts disabled, and returns with interrupts disabled.
Interrupts are enabled while the processor is asleep, but the interrupt
that wakes the processor is not handled; it is still pending when this
function returns.Signed-off-by: Scott Wood
Signed-off-by: Guennadi Liakhovetski
Signed-off-by: Paul Mackerras
17 Apr, 2008
1 commit
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Freescale UPM can be used to adjust localbus timings or to generate
orbitrary, pre-programmed "patterns" on the external Localbus signals.
This patch implements few routines so drivers could work with UPMs in
safe and generic manner.So far there is just one user of these routines: Freescale UPM NAND
driver.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala
26 Mar, 2008
1 commit
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This patch adds support for the 256k L2 cache found on some IBM/AMCC
4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c)
which currently "only" adds the L2 cache init code. Other common 4xx
stuff can be added later here.The L2 cache handling code is a copy of Eugene's code in arch/ppc
with small modifications.Tested on AMCC Taishan 440GX.
Signed-off-by: Stefan Roese
Signed-off-by: Josh Boyer
28 Jan, 2008
1 commit
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Rename commproc.[ch] to cpm1.[ch] to be more consistent with cpm2. Also
rename cpm2_common.c to cpm2.c as suggested by Scott Wood. Adjust the
includes accordingly.Signed-off-by: Jochen Friedrich
Signed-off-by: Kumar Gala
25 Jan, 2008
1 commit
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This patch extends the Ebony and Walnut platform code to instantiate
the existing ds1742 RTC class driver for the DS1743 RTC/NVRAM chip
found on both those boards. The patch uses a helper function to scan
the device tree and instantiate the appropriate platform_device based
on it, so it should be easy to extend for other boards which have mmio
mapped RTC chips.Along with this, the device tree binding for the ds1743 chips is
tweaked, based on the existing DS1385 OF binding found at:
http://playground.sun.com/1275/proposals/Closed/Remanded/Accepted/346-it.txt
Although that document covers the NVRAM portion of the chip, whereas
here we're interested in the RTC portion, so it's not entirely clear
if that's a good model.This implements only RTC class driver support - that is /dev/rtc0, not
/dev/rtc, and the low-level get/set time callbacks remain
unimplemented. That means in order to get at the clock you will
either need a modified version of hwclock which will look at
/dev/rtc0, or you'll need to configure udev to symlink rtc0 to rtc.Signed-off-by: David Gibson
Signed-off-by: Josh Boyer
24 Jan, 2008
2 commits
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Do just enough to move the RapidIO support code for 85xx over from arch/ppc
into arch/powerpc and make it still build.Signed-off-by: Kumar Gala
-
IPIC is not just for 83xx anymore so make it a separate config option.
Signed-off-by: John Rigby
Signed-off-by: Kumar Gala
24 Dec, 2007
1 commit
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This adds base support code for the 4xx PCI-X bridge. It also provides
placeholders for the PCI and PCI-E version but they aren't supported
with this patch.The bridges are configured based on device-tree properties.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Josh Boyer
20 Dec, 2007
1 commit
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Implement MSI support for PA Semi PWRficient platforms. MSI is done
through a special range of sources on the openpic controller, and they're
unfortunately breaking the usual concepts of how sources are programmed:* The source is calculated as 512 + the value written into the MSI
register
* The vector for this source is added to the source and reported
through IACKThis means that for simplicity, it makes much more sense to just set the
vector to 0 for the source, since that's really the vector we expect to
see from IACK.Also, the affinity/priority registers will affect 16 sources at a
time. To avoid most (simple) users from being limited by this, allocate
16 sources per device but use only one. This means that there's a total
of 32 sources.If we get usage scenarions that need more sources, the allocator should
probably be revised to take an alignment argument and size, not just do
natural alignment.Finally, since I'm already touching the MPIC names on pasemi, rename
the base one from the somewhat odd " PAS-OPIC " to "PASEMI-OPIC".Signed-off-by: Olof Johansson
Acked-by: Michael Ellerman
Signed-off-by: Paul Mackerras
17 Oct, 2007
1 commit
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This patch adds support for the core of the BestComm API
for the Freescale MPC5200(b). The BestComm engine is a
microcode-controlled / tasks-based DMA used by several
of the onchip devices.Setting up the tasks / memory allocation and all common
low level functions are handled by this patch.
The specifics details of each tasks and their microcode
are split-out in separate patches.This is not the official API, but a much cleaner one.
(hopefully)Signed-off-by: Sylvain Munaut
Signed-off-by: Grant Likely
10 Oct, 2007
1 commit
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dcr.c is an arch/powerpc only thing. Compiling ppc405 arch/ppc kernels
throws warnings without this change.Signed-off-by: Grant Likely
04 Oct, 2007
1 commit
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This code assumes that the ports have been previously set up, with
buffers in DPRAM.Signed-off-by: Scott Wood
Acked-by: David Gibson
Signed-off-by: Kumar Gala
03 Oct, 2007
2 commits
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Adds support for the Xilinx opb-intc interrupt controller
Signed-off-by: Grant Likely
Signed-off-by: Josh Boyer -
With these functions implemented we cooperate better with the generic
timekeeping code. This obsoletes the need for the timer sysdev as a bonus.Signed-off-by: Tony Breeds
Signed-off-by: Paul Mackerras
22 Sep, 2007
1 commit
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Commit 69331af, "Fixes and cleanups for earlyprintk aka boot console",
resulted in printk output prior to the initialization of the mpsc
console driver not being printed. That commit causes the mpsc's
CON_PRINTBUFFER flag to be cleared since udbg should have printed
the previous output.I guess we can no longer ignore udbg. :)
This patch provides udbg_putc() and udbg_getc() functions for the
Marvell mv64x60 chips. These functions are enabled if an mv64x60
port is to be used as the console as determined from the device tree.Signed-off-by: Dale Farnsworth
Acked-by: Mark A. Greer
Signed-off-by: Paul Mackerras
23 Jul, 2007
1 commit
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Move
arch/powerpc/platforms/86xx/pci.c -> arch/powerpc/sysdev/fsl_pci.c
arch/powerpc/sysdev/fsl_pcie.h -> arch/powerpc/sysdev/fsl_pci.h
as the base to unify 83xx/85xx/86xx pci and pcie.Add CONFIG_FSL_PCI to build fsl_pci.c for Freescale pci and pcie option.
The code still works for 86xx platforms.Signed-off-by: Roy Zang
Signed-off-by: Kumar Gala
