15 Mar, 2011

1 commit

• f4154e160   powerpc/fsl_pci: Add support for FSL PCIe controllers v2.x ... Browse Code »

  FSL PCIe controller v2.1:
  - New MSI inbound window
  - Same Inbound windows address as PCIe controller v1.x

  Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window

  FSL PCIe controller v2.2 and v2.3:
  - Different addresses for PCIe inbound window 3,2,1
  - Exposed PCIe inbound window 0
  - New PCIe interrupt status register

  Added new config and interrupt Status register to struct ccsr_pci & updated
  pit_t array size to reflect the 4 inbound windows.

  Device tree is used to maintain backward compatibility i.e. update inbound
  window 1 index depending upon "compatible" field witin PCIE node.

  Signed-off-by: Prabhakar Kushwaha
  Acked-by: Roy Zang
  Signed-off-by: Kumar Gala

  Prabhakar Kushwaha

  2011-03-15 22:29:56 +0800  

14 Oct, 2010

1 commit

• b8f44ec2c   powerpc/fsl-pci: Fix MSI support on 83xx platforms ... Browse Code »

  The following commit broke 83xx because it assumed the 83xx platforms
  exposed the "IMMR" address in BAR0 like the 85xx/86xx/QoriQ devices do:

  commit 3da34aae03d498ee62f75aa7467de93cce3030fd
  Author: Kumar Gala
  Date: Tue May 12 15:51:56 2009 -0500

  powerpc/fsl: Support unique MSI addresses per PCIe Root Complex

  However that is not true, so we have to search through the inbound
  window settings on 83xx to find which one matches the IMMR address to
  determine its PCI address.

  Reported-by: Ilya Yanok
  Signed-off-by: Kumar Gala

  Kumar Gala

  2010-10-14 13:52:30 +0800  

19 May, 2009

1 commit

• 54c181935   powerpc/fsl: Setup PCI inbound window based on actual amount of memory ... Browse Code »

  Previouslly we just always set the inbound window to 2G. This was
  broken for systems with >2G. If a system has >=4G we will need
  SWIOTLB support to handle that case.

  We now allocate PCICSRBAR/PEXCSRBAR right below the lowest PCI outbound
  address for MMIO or the 4G boundary (if the lowest PCI address is above
  4G).

  Signed-off-by: Kumar Gala

  Kumar Gala

  2009-05-19 13:50:44 +0800  

17 Jul, 2008

1 commit

• 76fe1ffce   powerpc: Move mpc83xx_add_bridge to fsl_pci.c ... Browse Code »

  This allows other platforms with the same pci block like MPC5121 to use it.

  Signed-off-by: John Rigby
  Acked-by: Grant Likely
  Signed-off-by: Kumar Gala

  John Rigby

  2008-07-17 06:57:35 +0800  

23 Jul, 2007

3 commits

• 6c0a11c11   [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected ... Browse Code »

  On the 85xx/86xx PCIe controllers if there is no device connected to the
  PHB we will still allocate a pci_bus for downstream bus of the virtual
  P2P bridge. However the resources allocated to the downstream bus are not
  correct and so we just mimic the resources from the upstream pci_bus.

  Signed-off-by: Kumar Gala

  Kumar Gala

  2007-07-23 23:27:08 +0800  
• 9ac4dd301   [POWERPC] Rewrite Freescale PCI/PCIe support for 8{3,5,6}xx ... Browse Code »

  Rewrite the Freescale PCI code to support PCI on 83xx/85xx/86xx and
  PCIe on 85xx/86xx.

  Signed-off-by: Roy Zang
  Signed-off-by: Kumar Gala

  Zang Roy-r61911

  2007-07-23 23:27:07 +0800  
• 55c44991e   [POWERPC] Create common fsl pci/e files based on 86xx platforms ... Browse Code »

  Move
  arch/powerpc/platforms/86xx/pci.c -> arch/powerpc/sysdev/fsl_pci.c
  arch/powerpc/sysdev/fsl_pcie.h -> arch/powerpc/sysdev/fsl_pci.h
  as the base to unify 83xx/85xx/86xx pci and pcie.

  Add CONFIG_FSL_PCI to build fsl_pci.c for Freescale pci and pcie option.
  The code still works for 86xx platforms.

  Signed-off-by: Roy Zang
  Signed-off-by: Kumar Gala

  Roy Zang

  2007-07-23 23:27:07 +0800