10 Oct, 2011
2 commits
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This patch implements IBS feature detection and initialzation. The
code is shared between perf and oprofile. If IBS is available on the
system for perf, a pmu is setup.Signed-off-by: Robert Richter
Signed-off-by: Peter Zijlstra
Link: http://lkml.kernel.org/r/1316597423-25723-3-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar -
Moving IBS macros from oprofile to to make it
available to perf. No additional changes.Signed-off-by: Robert Richter
Signed-off-by: Peter Zijlstra
Link: http://lkml.kernel.org/r/1316597423-25723-2-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar
30 May, 2011
1 commit
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Adding a comment in the code as IBS LVT setup is not obvious at all ...
Signed-off-by: Robert Richter
20 May, 2011
1 commit
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IBS initialization is a mix of per-core register access and per-node
pci device setup. Register access should be pinned to the cpu, but pci
setup must run with preemption enabled.This patch better separates the code into non-/preemptible sections
and fixes sleeping with preemption disabled. See bug message below.Fixes also freeing the eilvt entry by introducing put_eilvt().
BUG: sleeping function called from invalid context at mm/slub.c:824
in_atomic(): 1, irqs_disabled(): 0, pid: 32357, name: modprobe
INFO: lockdep is turned off.
Pid: 32357, comm: modprobe Not tainted 2.6.39-rc7+ #14
Call Trace:
[] __might_sleep+0x112/0x117
[] kmem_cache_alloc_trace+0x4b/0xe7
[] kzalloc.constprop.0+0x29/0x2b
[] pci_get_subsys+0x36/0x78
[] ? setup_APIC_eilvt+0xfb/0x139
[] pci_get_device+0x16/0x18
[] op_amd_init+0xd3/0x211 [oprofile]
[] ? 0xffffffffa064cfff
[] op_nmi_init+0x21e/0x26a [oprofile]
[] oprofile_arch_init+0xe/0x26 [oprofile]
[] oprofile_init+0x10/0x42 [oprofile]
[] do_one_initcall+0x7f/0x13a
[] sys_init_module+0x132/0x281
[] system_call_fastpath+0x16/0x1bReported-by: Dave Jones
Cc: [2.6.37.x]
Signed-off-by: Robert Richter
07 Jan, 2011
1 commit
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* 'x86-mce-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
apic, amd: Make firmware bug messages more meaningful
mce, amd: Remove goto in threshold_create_device()
mce, amd: Add helper functions to setup APIC
mce, amd: Shorten local variables mci_misc_{hi,lo}
mce, amd: Implement mce_threshold_block_init() helper function
05 Jan, 2011
1 commit
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Merge reason: Add the final .37 tree.
Signed-off-by: Ingo Molnar
03 Jan, 2011
1 commit
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Disable preemption in init_ibs(). The function only checks the
ibs capabilities and sets up pci devices (if necessary). It runs
only on one cpu but operates with the local APIC and some MSRs,
thus it is better to disable preemption.[ 7.034377] BUG: using smp_processor_id() in preemptible [00000000] code: modprobe/483
[ 7.034385] caller is setup_APIC_eilvt+0x155/0x180
[ 7.034389] Pid: 483, comm: modprobe Not tainted 2.6.37-rc1-20101110+ #1
[ 7.034392] Call Trace:
[ 7.034400] [] debug_smp_processor_id+0xd2/0xf0
[ 7.034404] [] setup_APIC_eilvt+0x155/0x180
[ ... ]Addresses https://bugzilla.kernel.org/show_bug.cgi?id=22812
Reported-by:
Signed-off-by: Robert Richter
Cc: oprofile-list@lists.sourceforge.net
Cc: Peter Zijlstra
Cc: Frederic Weisbecker
Cc: Rafael J. Wysocki
Cc: Dan Carpenter
Cc: Andrew Morton
Cc: [2.6.37.x]
LKML-Reference:
[ small cleanups ]
Signed-off-by: Ingo Molnar
19 Dec, 2010
1 commit
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This patch adds support for up to 6 hardware counters for AMD family
15h cpus. There is a new MSR range for hardware counters beginning at
MSRC001_0200 Performance Event Select (PERF_CTL0).Signed-off-by: Robert Richter
26 Oct, 2010
2 commits
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This improves error messages in case the BIOS was setting up
wrong LVT offsets.Signed-off-by: Robert Richter
Acked-by: Borislav Petkov
LKML-Reference:
Signed-off-by: Ingo Molnar
25 Oct, 2010
2 commits
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Conflicts:
arch/x86/oprofile/op_model_amd.cSigned-off-by: Robert Richter
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Stephen Rothwell reported this build warning:
arch/x86/oprofile/op_model_amd.c: In function 'ibs_eilvt_valid':
arch/x86/oprofile/op_model_amd.c:289: warning: 'offset' may be used uninitialized in this functionAnd correctly observed that indeed the variable is used uninitialized in
this function. The result of this bug can be a debug printk with a bogus
value.Also fix a few more small details that made this function hard to read
and which probably contributed to the bug being introduced to begin with:- Use more symmetric error conditions
- Remove the !0 obfuscation
- Add newlines to the printk output
- Remove bogus linebreaks in printk strings and elsewhere
Reported-by: Stephen Rothwell
Cc: Robert Richter
Cc: Linus Torvalds
LKML-Reference:
Signed-off-by: Ingo Molnar
20 Oct, 2010
1 commit
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We want the BIOS to setup the EILVT APIC registers. The offsets
were hardcoded and BIOS settings were overwritten by the OS.
Now, the subsystems for MCE threshold and IBS determine the LVT
offset from the registers the BIOS has setup. If the BIOS setup
is buggy on a family 10h system, a workaround enables IBS. If
the OS determines an invalid register setup, a "[Firmware Bug]:
" error message is reported.We need this change also for upcomming cpu families.
Signed-off-by: Robert Richter
LKML-Reference:
Signed-off-by: Ingo Molnar
15 Oct, 2010
5 commits
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The count value for IBS op sampling has been extended by 7 bits. The
feature is reflected in bit 6 (OpCntExt) of the IBS capability
register (CPUID Fn8000_001B_EAX).Signed-off-by: Robert Richter
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This patch adds support for IBS branch target address reporting. A new
MSR (MSRC001_103B IBS Branch Target Address) has been added that
provides the logical address in canonical form for the branch
target. The size of the IBS sample that is transferred to the userland
has been increased.For backward compatibility, the userland daemon must explicit enable
the feature by writing to the oprofilefs fileibs_op/branch_target
After enabling branch target address reporting, the userland daemon
must handle the extended size of the IBS sample.Signed-off-by: Robert Richter
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This patch introduces struct ibs_state that will extended by additinal
members in follow-on patches.Signed-off-by: Robert Richter
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Since oprofile is setting up ibs_op/dispatched_ops in the fs only if
the feature is available, its corresponding variable
ibs_config.dispatched_ops is only set, if the feature is
available. Thus the check is duplicate and can be removed.Signed-off-by: Robert Richter
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There are IBS CPUID feature flags in CPUID Fn8000_001B to detect if
the cpu supports IBS fetch sampling (FetchSam) and/or IBS execution
sampling (OpSam). This patch adds checks if the both features are
available.Spec:
http://support.amd.com/us/Processor_TechDocs/31116.pdf
Signed-off-by: Robert Richter
06 May, 2010
1 commit
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Current IBS code is not hotplug capable. An offline cpu might not be
initialized or deinitialized properly. This patch fixes this by
removing on_each_cpu() functions. The IBS init/deinit code is executed
in the per-cpu functions model->setup_ctrs() and model->cpu_down()
which are also called by hotplug notifiers. model->cpu_down() replaces
model->exit() that became obsolete.Cc: Andi Kleen
Signed-off-by: Robert Richter
04 May, 2010
5 commits
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The check is already done in ibs_exit().
Signed-off-by: Robert Richter
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Moving code to make future changes easier. This groups all IBS code
together.Signed-off-by: Robert Richter
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In case a counter is already reserved by the watchdog or perf_event
subsystem, oprofile ignored this counters silently. This case is
handled now and oprofile_setup() now reports an error.Signed-off-by: Robert Richter
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Moving some code in preparation of the next patch.
Signed-off-by: Robert Richter
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For AMD's and Intel's P6 generic performance counters have pairwise
counter and control msrs. This patch changes the counter reservation
in a way that both msrs must be registered. It joins some counter
loops and also removes the unnecessary NUM_CONTROLS macro in the AMD
implementation.Signed-off-by: Robert Richter
01 Mar, 2010
3 commits
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For consistency reasons this patch renames
ARCH_PERFMON_EVENTSEL0_ENABLE to ARCH_PERFMON_EVENTSEL_ENABLE.The following is performed:
$ sed -i -e s/ARCH_PERFMON_EVENTSEL0_ENABLE/ARCH_PERFMON_EVENTSEL_ENABLE/g \
arch/x86/include/asm/perf_event.h arch/x86/kernel/cpu/perf_event.c \
arch/x86/kernel/cpu/perf_event_p6.c \
arch/x86/kernel/cpu/perfctr-watchdog.c \
arch/x86/oprofile/op_model_amd.c arch/x86/oprofile/op_model_ppro.cSigned-off-by: Robert Richter
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Signed-off-by: Robert Richter
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This patch moves code from oprofile to perf_event.h to make it also
available for usage by perf.Signed-off-by: Robert Richter
26 Feb, 2010
9 commits
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During switching virtual counters there is access to perfctr msrs. If
the counter is not available this fails due to an invalid
address. This patch fixes this.Cc: stable@kernel.org
Signed-off-by: Robert Richter -
Cc: stable@kernel.org
Signed-off-by: Robert Richter -
Multiple virtual counters share one physical counter. The reservation
of virtual counters fails due to duplicate allocation of the same
counter. The counters are already reserved. Thus, virtual counter
reservation may removed at all. This also makes the code easier.Cc: stable@kernel.org
Signed-off-by: Robert Richter -
This patch generates a warning if a counter is already active.
Implemented for AMD and P6 models. P4 is not supported.
Cc: Naga Chumbalkar
Cc: Shashi Belur
Cc: Tony Jones
Signed-off-by: Robert Richter -
IBS selects an op (execution operation) for sampling by counting
either cycles or dispatched ops. Better statistical samples can be
produced by adding a software generated random offset to the periodic
op counter value with each sample.This patch adds software randomization to the IBS periodic op
counter. The lower 12 bits of the 20 bit counter are
randomized. IbsOpCurCnt is initialized with a 12 bit random value.There is a work around if the hw can not write to IbsOpCurCnt. Then
the lower 8 bits of the 16 bit IbsOpMaxCnt [15:0] value are randomized
in the range of -128 to +127 by adding/subtracting an offset to the
maximum count (IbsOpMaxCnt).The linear feedback shift register (LFSR) algorithm is used for
pseudo-random number generation to have low impact to the memory
system.Signed-off-by: Robert Richter
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This patch implements a linear feedback shift register (LFSR) for
pseudo-random number generation for IBS.For IBS measurements it would be good to minimize memory traffic in
the interrupt handler since every access pollutes the data
caches. Computing a maximal period LFSR just needs shifts and ORs.The LFSR method is good enough to randomize the ops at low
overhead. 16 pseudo-random bits are enough for the implementation and
it doesn't matter that the pattern repeats with a fairly short
cycle. It only needs to break up (hard) periodic sampling behavior.The logic was designed by Paul Drongowski.
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Robert Richter -
This patch adds IBS feature detection using cpuid flags. An IBS
capability mask is introduced to test for certain IBS features. The
bit mask is the same as for IBS cpuid feature flags (Fn8000_001B_EAX),
but bit 0 is used to indicate the existence of IBS.The patch also changes the handling of the IbsOpCntCtl bit (periodic
op counter count control). The oprofilefs file for this feature
(ibs_op/dispatched_ops) will be only exposed if the feature is
available, also the default for the bit is set to count clock cycles.In general, the userland can detect the availability of a feature by
checking for the corresponding file in oprofilefs. If it exists, the
feature also exists. This may lead to a dynamic file layout depending
on the cpu type with that the userland has to deal with. Current
opcontrol is compatible.Signed-off-by: Robert Richter
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Standard AMD systems have the same number of nodes as there are
northbridge devices. However, there may kernel configurations
(especially for 32 bit) or system setups exist, where the node number
is different or it can not be detected properly. Thus the check is not
reliable and may fail though IBS setup was fine. For this reason it is
better to remove the check.Cc: stable
Signed-off-by: Robert Richter -
OProfile support for IBS is now for several versions in the
kernel. The feature is stable now and the code can be activated
permanently.As a side effect IBS now works also on nosmp configs.
Signed-off-by: Robert Richter
04 Aug, 2009
2 commits
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arch/x86/oprofile/op_model_amd.c: In function 'op_amd_handle_ibs':
arch/x86/oprofile/op_model_amd.c:217: warning: no return statement in function returning non-voidFix this by making op_amd_handle_ibs() return void.
Cc: Robert Richter
Signed-off-by: Andrew Morton
Signed-off-by: Robert Richter -
This reverts commit 21e70878215f620fe99ea7d7c74bc641aeec932f.
Instead Andrew's patch will be applied he posted at the same time.
Signed-off-by: Robert Richter
20 Jul, 2009
2 commits
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Some small coding style fixes.
Signed-off-by: Robert Richter
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This patch implements a common x86 function to convert virtual counter
numbers to physical.Signed-off-by: Robert Richter