12 Jan, 2012
1 commit
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We only need amd_bus.o for AMD systems with PCI. arch/x86/pci/Makefile
already depends on CONFIG_PCI=y, so this patch just adds the dependency
on CONFIG_AMD_NB.Cc: Yinghai Lu
Cc: stable@kernel.org # 2.6.34+ (needs adjustment for k8 -> amd rename)
Signed-off-by: Bjorn Helgaas
Signed-off-by: Linus Torvalds
18 Dec, 2011
1 commit
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This sets all up the other bits that need to be INTEL_MID
specific rather than Moorestown specific.Signed-off-by: Alan Cox
Link: http://lkml.kernel.org/r/20111217174318.7207.91543.stgit@bob.linux.org.uk
Signed-off-by: Ingo Molnar
12 Nov, 2010
1 commit
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This patch provides access methods for PCI registers that mis-behave on
the CE4100. Each register can be assigned a private init, read and
write routine. The exception to this is the bridge device. The
bridge device is the only device on bus zero (0) that requires any
fixup so it is a special case.[ tglx: minor coding style cleanups, __init annotation and
simplification of ce4100_conf_read/write ]Signed-off-by: Dirk Brandewie
LKML-Reference:
Signed-off-by: Thomas Gleixner
18 Oct, 2010
1 commit
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The frontend stub lives in arch/x86/pci/xen.c, alongside other
sub-arch PCI init code (e.g. olpc.c).It provides a mechanism for Xen PCI frontend to setup/destroy
legacy interrupts, MSI/MSI-X, and PCI configuration operations.[ Impact: add core of Xen PCI support ]
[ v2: Removed the IOMMU code and only focusing on PCI.]
[ v3: removed usage of pci_scan_all_fns as that does not exist]
[ v4: introduced pci_xen value to fix compile warnings]
[ v5: squished fixes+features in one patch, changed Reviewed-by to Ccs]
[ v7: added Acked-by]
Signed-off-by: Alex Nixon
Signed-off-by: Jeremy Fitzhardinge
Signed-off-by: Ian Campbell
Signed-off-by: Konrad Rzeszutek Wilk
Signed-off-by: Stefano Stabellini
Acked-by: Jesse Barnes
Cc: "H. Peter Anvin"
Cc: Matthew Wilcox
Cc: Qing He
Cc: Thomas Gleixner
Cc: x86@kernel.org
22 May, 2010
1 commit
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Read the memory ranges behind the Broadcom CNB20LE host bridge out of the
hardware. This allows PCI hotplugging to work, since we know which memory
range to allocate PCI BAR's from.The x86 PCI code automatically prefers the ACPI _CRS information when it is
available. In that case, this information is not used.Signed-off-by: Ira W. Snyder
Signed-off-by: Jesse Barnes
08 Mar, 2010
1 commit
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* 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (30 commits)
x86, mrst: Fix whitespace breakage in apb_timer.c
x86, mrst: Fix APB timer per cpu clockevent
x86, mrst: Remove X86_MRST dependency on PCI_IOAPIC
x86, olpc: Use pci subarch init for OLPC
x86, pci: Add arch_init to x86_init abstraction
x86, mrst: Add Kconfig dependencies for Moorestown
x86, pci: Exclude Moorestown PCI code if CONFIG_X86_MRST=n
x86, numaq: Make CONFIG_X86_NUMAQ depend on CONFIG_PCI
x86, pci: Add sanity check for PCI fixed bar probing
x86, legacy_irq: Remove duplicate vector assigment
x86, legacy_irq: Remove left over nr_legacy_irqs
x86, mrst: Platform clock setup code
x86, apbt: Moorestown APB system timer driver
x86, mrst: Add vrtc platform data setup code
x86, mrst: Add platform timer info parsing code
x86, mrst: Fill in PCI functions in x86_init layer
x86, mrst: Add dummy legacy pic to platform setup
x86/PCI: Moorestown PCI support
x86, ioapic: Add dummy ioapic functions
x86, ioapic: Early enable ioapic for timer irq
...Fixed up semantic conflict of new clocksources due to commit
17622339af25 ("clocksource: add argument to resume callback").
26 Feb, 2010
1 commit
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If we don't have any Moorestown CPU support compiled in, we don't need
the Moorestown PCI support either.Signed-off-by: Yinghai Lu
LKML-Reference:
Signed-off-by: H. Peter Anvin
24 Feb, 2010
1 commit
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The Moorestown platform only has a few devices that actually support
PCI config cycles. The rest of the devices use an in-RAM MCFG space
for the purposes of device enumeration and initialization.There are a few uglies in the fake support, like BAR sizes that aren't
a power of two, sizing detection, and writes to the real devices, but
other than that it's pretty straightforward.Another way to think of this is not really as PCI at all, but just a
table in RAM describing which devices are present, their capabilities
and their offsets in MMIO space. This could have been done with a
special new firmware table on this platform, but given that we do have
some real PCI devices too, simply describing things in an MCFG type
space was pretty simple.Signed-off-by: Jesse Barnes
LKML-Reference:
Signed-off-by: Jacob Pan
Signed-off-by: H. Peter Anvin
11 Feb, 2010
1 commit
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Should be good for 32bit too.
-v3: cast res->start
-v4: according to Linus, to use %pR instead of castSigned-off-by: Yinghai Lu
LKML-Reference:
Acked-by: Jesse Barnes
Signed-off-by: H. Peter Anvin
29 Jan, 2010
1 commit
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Turned out to cause trouble on single IOH machines, and is superceded by
_CRS on multi-IOH machines with production BIOSes.Signed-off-by: Jeff Garrett
Signed-off-by: Jesse Barnes
25 Nov, 2009
1 commit
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Those functions are used by intel_bus.c so seperate them to another file. and
make amd_bus a bit smaller.Signed-off-by: Yinghai Lu
Signed-off-by: Jesse Barnes
05 Nov, 2009
2 commits
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We use dev_dbg() in arch/x86/pci, but there's no easy way to turn it
on. Add -DDEBUG when CONFIG_PCI_DEBUG=y, just like we do in drivers/pci.Signed-off-by: Bjorn Helgaas
Signed-off-by: Jesse Barnes -
For intel systems with multi IOH, we should read peer root resources
directly from PCI config space, and don't trust _CRS.Signed-off-by: Yinghai Lu
Signed-off-by: Jesse Barnes
12 Jul, 2008
2 commits
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Cc: Yinghai Lu
Signed-off-by: Robert Richter
Cc: Robert Richter
Cc: Yinghai Lu
Signed-off-by: Ingo Molnar -
Cc: Sam Ravnborg
Signed-off-by: Robert Richter
Cc: Robert Richter
Cc: Sam Ravnborg
Signed-off-by: Ingo Molnar
11 Jul, 2008
3 commits
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remove leftover arch/x86/mach-visws/* files.
Signed-off-by: Ingo Molnar
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add early init quirks for VisWS. This gradually turns the VISWS subarch
into a generic PC architecture.Signed-off-by: Ingo Molnar
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first step: make the VISWS subarch boot on a regular PC.
We take various shortcuts for that. We copy the generic arch setup file over
into the VISWS setup file.This is the only step that is not expected to boot on a real VISWS.
Signed-off-by: Ingo Molnar
09 Jul, 2008
9 commits
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So far subsys_initcalls has been executed in this order depending on
the object order in the Makefile:arch/x86/pci/visws.c:subsys_initcall(pcibios_init);
arch/x86/pci/numa.c:subsys_initcall(pci_numa_init);
arch/x86/pci/acpi.c:subsys_initcall(pci_acpi_init);
arch/x86/pci/legacy.c:subsys_initcall(pci_legacy_init);
arch/x86/pci/irq.c:subsys_initcall(pcibios_irq_init);
arch/x86/pci/common.c:subsys_initcall(pcibios_init);This patch removes the ordering dependency. There is now only one
subsys_initcall function that contains subsystem initialization code
with a defined order.Signed-off-by: Robert Richter
Acked-by: Jesse Barnes
Signed-off-by: Ingo Molnar -
Signed-off-by: Robert Richter
Acked-by: Jesse Barnes
Signed-off-by: Ingo Molnar -
Signed-off-by: Robert Richter
Acked-by: Jesse Barnes
Signed-off-by: Ingo Molnar -
Signed-off-by: Robert Richter
Acked-by: Jesse Barnes
Signed-off-by: Ingo Molnar -
This should be safe since mmconfig*.o and init.o do not contain
*initcalls with the same level as in other files.Signed-off-by: Robert Richter
Acked-by: Jesse Barnes
Signed-off-by: Ingo Molnar -
Signed-off-by: Robert Richter
Acked-by: Jesse Barnes
Signed-off-by: Ingo Molnar -
Signed-off-by: Robert Richter
Acked-by: Jesse Barnes
Signed-off-by: Ingo Molnar -
Signed-off-by: Robert Richter
Acked-by: Jesse Barnes
Signed-off-by: Ingo Molnar -
No functional nor ordering changes here.
Signed-off-by: Robert Richter
Acked-by: Jesse Barnes
Signed-off-by: Ingo Molnar
11 Oct, 2007
2 commits
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Signed-off-by: Thomas Gleixner
Signed-off-by: Ingo Molnar -
Signed-off-by: Thomas Gleixner
Signed-off-by: Ingo Molnar
