04 Jan, 2012

2 commits

  • These registers are automatically incremented by the hardware during
    transform feedback to track where the next streamed vertex output
    should go. Unlike the previous generation, which had a packet for
    setting the corresponding registers to a defined value, gen7 only has
    MI_LOAD_REGISTER_IMM to do so. That's a secure packet (since it loads
    an arbitrary register), so we need to do it from the kernel, and it
    needs to be settable atomically with the batchbuffer execution so that
    two clients doing transform feedback don't stomp on each others'
    state.

    Instead of building a more complicated interface involcing setting the
    registers to a specific value, just set them to 0 when asked and
    userland can tweak its pointers accordingly.

    Signed-off-by: Eric Anholt
    Reviewed-by: Eugeni Dodonov
    Reviewed-by: Kenneth Graunke
    Signed-off-by: Keith Packard

    Eric Anholt
     
  • Add new ioctls for getting and setting the current destination color
    key. This allows for simple overlay display control by matching a color
    key value in the primary plane before blending the overlay on top.

    v2: remove unnecessary mutex acquire/release around reg accesses
    v3: add support for full color key management
    v4: fix copy & paste bug in snb_get_colorkey
    don't bother checking min/max values against docs as the docs are likely
    wrong (how could we handle 10bpc surface formats?)

    Reviewed-by: Daniel Vetter
    Signed-off-by: Jesse Barnes

    Jesse Barnes
     

23 Jul, 2011

1 commit

  • Because of a typo, calling ioctl with DRM_IOCTL_I915_OVERLAY_PUT_IMAGE
    is broken if the macro is used directly. When using libdrm the bug is
    not hit, since libdrm handles the ioctl encoding internally.

    The typo also leads to the .cmd and .cmd_drv fields of the drm_ioctl
    structure for DRM_I915_OVERLAY_PUT_IMAGE having inconsistent content.

    Signed-off-by: Ole Henrik Jahren
    Acked-by: Daniel Vetter
    Cc: stable@kernel.org
    Signed-off-by: Keith Packard

    Ole Henrik Jahren
     

02 Mar, 2011

1 commit


20 Dec, 2010

1 commit


05 Dec, 2010

1 commit

  • Otherwise we can't really fix the abi-braindeadness of forcing
    libva to manually wait for rendering when switching rings. Which
    in turn makes implementing hw semaphores a pointless exercise
    (at least for ironlake).

    [Also added the relaxed fencing param to explain the jump in
    numbering - relaxed fencing is in -next.]

    Signed-off-by: Daniel Vetter
    Signed-off-by: Chris Wilson

    Daniel Vetter
     

22 Oct, 2010

1 commit


24 Aug, 2010

1 commit

  • * 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (33 commits)
    drm/radeon/kms: fix typo in radeon_compute_pll_gain
    drm/radeon/kms: try to detect tv vs monitor for underscan
    drm/radeon/kms: fix sideport detection on newer rs880 boards
    drm/radeon: fix passing wrong type to gem object create.
    drm/radeon/kms: set encoder type to DVI for HDMI on evergreen
    drm/radeon/kms: add back missing break in info ioctl
    drm/radeon/kms: don't enable MSIs on AGP boards
    drm/radeon/kms: fix agp mode setup on cards that use pcie bridges
    drm: move dereference below check
    drm: fix end of loop test
    drm/radeon/kms: rework radeon_dp_detect() logic
    drm/radeon/kms: add missing asic callback assignment for evergreen
    drm/radeon/kms/DCE3+: switch pads to ddc mode when going i2c
    drm/radeon/kms/pm: bail early if nothing's changing
    drm/radeon/kms/atom: clean up dig atom handling
    drm/radeon/kms: DCE3/4 transmitter fixes
    drm/radeon/kms: rework encoder handling
    drm/radeon/kms: DCE3/4 AdjustPixelPll updates
    drm/radeon: Fix stack data leak
    drm/radeon/kms: fix GTT/VRAM overlapping test
    ...

    Linus Torvalds
     

17 Aug, 2010

1 commit

  • With the current screwed but its ABI, ioctls for the drm, Linus pointed out that we could allow userspace to specify the allocation size, but we pass it to the driver which then uses it blindly to store a struct. Now if userspace specifies the allocation size as smaller than the driver needs, the driver can possibly overwrite memory.

    This patch restructures the driver ioctls so we store the structure size we are expecting, and make sure we allocate at least that size. The copy from/to userspace are still restricted to the size the user specifies, this allows ioctl structs to grow on both sides of the equation.

    Up until now we didn't really use the DRM_IOCTL defines in the kernel, so this cleans them up and adds them for nouveau.

    v2:
    fix nouveau pushbuf arg (thanks to Ben for pointing it out)

    Reported-by: Linus Torvalds
    Signed-off-by: Dave Airlie

    Dave Airlie
     

03 Aug, 2010

1 commit

  • Intel Core i3/5 platforms with integrated graphics support both CPU and
    GPU turbo mode. CPU turbo mode is opportunistic: the CPU will use any
    available power to increase core frequencies if thermal headroom is
    available. The GPU side is more manual however; the graphics driver
    must monitor GPU power and temperature and coordinate with a core
    thermal driver to take advantage of available thermal and power headroom
    in the package.

    The intelligent power sharing (IPS) driver is intended to coordinate
    this activity by monitoring MCP (multi-chip package) temperature and
    power, allowing the CPU and/or GPU to increase their power consumption,
    and thus performance, when possible. The goal is to maximize
    performance within a given platform's TDP (thermal design point).

    Signed-off-by: Jesse Barnes
    Signed-off-by: Matthew Garrett

    Jesse Barnes
     

02 Jun, 2010

1 commit


27 May, 2010

1 commit

  • Introduces a more complete intel_ring_buffer structure with callbacks
    for setup and management of a particular ringbuffer, and converts the
    render ring buffer consumers to use it.

    Signed-off-by: Zou Nan hai
    Signed-off-by: Xiang Hai hao
    [anholt: Fixed up whitespace fail and rebased against prep patches]
    Signed-off-by: Eric Anholt

    Zou Nan hai
     

07 Jan, 2010

1 commit

  • This patch adds a new execbuf ioctl, execbuf2, for use by clients that
    want to control fence register allocation more finely. The buffer
    passed in to the new ioctl includes a new relocation type to indicate
    whether a given object needs a fence register assigned for the command
    buffer in question.

    Compatibility with the existing execbuf ioctl is implemented in terms
    of the new code, preserving the assumption that fence registers are
    required for pre-965 rendering commands.

    Signed-off-by: Jesse Barnes
    [ickle: Remove pre-emptive clear_fence_reg()]
    Signed-off-by: Chris Wilson
    Signed-off-by: Kristian Høgsberg
    [anholt: Removed dmesg spam]
    Signed-off-by: Eric Anholt

    Jesse Barnes
     

08 Dec, 2009

1 commit


04 Dec, 2009

1 commit


02 Dec, 2009

2 commits


06 Nov, 2009

1 commit

  • This implements intel overlay support for kms via a device-specific
    ioctl. Thomas Hellstrom brought up the idea of a general ioctl (on
    dri-devel). We've reached the conclusion that such an infrastructure
    only makes sense when multiple kms overlay implementations exists,
    which atm don't (and it doesn't look like this is gonna change).

    Open issues:
    - Runs in sync with the gpu, i.e. unnecessary waiting. I've decided
    to wait on this because the hw tends to hang when changing something
    in this area. I left some dummy functions as infrastructure.
    - polyphase filtering uses a static table.
    - uses uninterruptible sleeps. Unfortunately the alternatives may
    unnecessarily wedged the hw if/when we timeout too early (and
    userspace only overloaded the batch buffers with stuff worth a few
    secs of gpu time).

    Changes since v1:
    - fix off-by-one misconception on my side. This fixes fullscreen
    playback.
    Changes since v2:
    - add underrun detection as spec'ed for i965.
    - flush caches properly, fixing visual corruptions.
    Changes since v4:
    - fix up cache flushing of overlay memory regs.
    - killed require_pipe_a logic - it hangs the chip.

    Tested-By: diego.abelenda@gmail.com (on a 865G)
    Signed-off-by: Daniel Vetter
    [anholt: Resolved against the MADVISE ioctl going in before this one]
    Signed-off-by: Eric Anholt

    Daniel Vetter
     

23 Sep, 2009

1 commit


18 Sep, 2009

1 commit

  • Similar to the madvise() concept, the application may wish to mark some
    data as volatile. That is in the event of memory pressure the kernel is
    free to discard such buffers safe in the knowledge that the application
    can recreate them on demand, and is simply using these as a cache.

    Signed-off-by: Chris Wilson
    Signed-off-by: Jesse Barnes

    Chris Wilson
     

15 May, 2009

1 commit

  • This allows userlevel code to discover the pipe number corresponding
    to a given CRTC ID. This is necessary for doing pipe-specific
    operations such as waiting for vblank on a given CRTC. Failure to use
    the right pipe mapping can result in GPU hangs, or at least failure
    to actually sync to vblank.

    Signed-off-by: Carl Worth
    [anholt: Style touchups from review]
    Signed-off-by: Eric Anholt

    Carl Worth
     

09 Apr, 2009

1 commit

  • Save the bit 17 state of the pages when freeing the page list, and
    reswizzle them if necessary when rebinding the pages (in case they were
    swapped out). Since we have userland with expectations that the swizzle
    enums let it pread and pwrite contents accurately, we can't expose a new
    swizzle enum for bit 17 (which it would have to GTT map to handle), so we
    handle it down in pread and pwrite by swizzling the copy when bit 17 of the
    page address is set.

    Signed-off-by: Eric Anholt

    Eric Anholt
     

27 Mar, 2009

2 commits


08 Feb, 2009

1 commit

  • Adds code to set up fence registers at execbuf time on pre-965 chips as
    necessary. Also fixes up a few bugs in the pre-965 tile register support
    (get_order != ffs). The number of fences available to the kernel defaults
    to the hw limit minus 3 (for legacy X front/back/depth), but a new parameter
    allows userspace to override that as needed.

    Signed-off-by: Jesse Barnes
    Signed-off-by: Eric Anholt
    Signed-off-by: Dave Airlie

    Jesse Barnes
     

29 Dec, 2008

4 commits

  • fdo bug #19132.

    Signed-off-by: Eric Anholt
    Signed-off-by: Dave Airlie

    Eric Anholt
     
  • Painfully userspace started using new names that were never actually to be
    used from the external repo.

    Also fill out the gaps in the structure for old/new userspace compat

    Add compat defines for these structs.

    Signed-off-by: Dave Airlie

    Dave Airlie
     
  • This commit adds i915 driver support for the DRM mode setting APIs.
    Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
    supported. HDMI, DisplayPort and additional SDVO output support will
    follow.

    Support for the mode setting code is controlled by the new 'modeset'
    module option. A new config option, CONFIG_DRM_I915_KMS controls the
    default behavior, and whether a PCI ID list is built into the module for
    use by user level module utilities.

    Note that if mode setting is enabled, user level drivers that access
    display registers directly or that don't use the kernel graphics memory
    manager will likely corrupt kernel graphics memory, disrupt output
    configuration (possibly leading to hangs and/or blank displays), and
    prevent panic/oops messages from appearing. So use caution when
    enabling this code; be sure your user level code supports the new
    interfaces.

    A new SysRq key, 'g', provides emergency support for switching back to
    the kernel's framebuffer console; which is useful for testing.

    Co-authors: Dave Airlie , Hong Liu

    Signed-off-by: Jesse Barnes
    Signed-off-by: Eric Anholt
    Signed-off-by: Dave Airlie

    Jesse Barnes
     
  • Use the new core GEM object mapping code to allow GTT mapping of GEM
    objects on i915. The fault handler will make sure a fence register is
    allocated too, if the object in question is tiled.

    Signed-off-by: Jesse Barnes
    Signed-off-by: Eric Anholt
    Signed-off-by: Dave Airlie

    Jesse Barnes
     

03 Nov, 2008

1 commit


18 Oct, 2008

2 commits

  • Signed-off-by: Kristian Høgsberg
    Signed-off-by: Eric Anholt
    Signed-off-by: Dave Airlie

    Kristian Høgsberg
     
  • GEM allows the creation of persistent buffer objects accessible by the
    graphics device through new ioctls for managing execution of commands on the
    device. The userland API is almost entirely driver-specific to ensure that
    any driver building on this model can easily map the interface to individual
    driver requirements.

    GEM is used by the 2d driver for managing its internal state allocations and
    will be used for pixmap storage to reduce memory consumption and enable
    zero-copy GLX_EXT_texture_from_pixmap, and in the 3d driver is used to enable
    GL_EXT_framebuffer_object and GL_ARB_pixel_buffer_object.

    Signed-off-by: Eric Anholt
    Signed-off-by: Dave Airlie

    Eric Anholt
     

14 Jul, 2008

1 commit

  • With the coming of kernel based modesetting and the memory manager stuff,
    the everything in one directory approach was getting very ugly and
    starting to be unmanageable.

    This restructures the drm along the lines of other kernel components.

    It creates a drivers/gpu/drm directory and moves the hw drivers into
    subdirectores. It moves the includes into an include/drm, and
    sets up the unifdef for the userspace headers we should be exporting.

    Signed-off-by: Dave Airlie

    Dave Airlie