11 May, 2011

1 commit


29 Jul, 2010

2 commits

  • Platform parameter to enable automatic FIFO configuration when
    the codec is in Mode1 or Mode7 FIFO mode.
    When this mode is selected, the controls for changing
    nSample (in Mode1), and UTHR (in Mode7) are not added.
    The driver configures the FIFO configuration based on
    the stream's period size in a way, that every burst will
    read period size of data from the host.
    In Mode7 we need to use a formula, which gives close enough
    aproximation for the burst length from the host point
    of view.

    Signed-off-by: Peter Ujfalusi
    Acked-by: Mark Brown
    Signed-off-by: Liam Girdwood

    Peter Ujfalusi
     
  • Replace the hardwired latency definition with platform data
    parameter, and simplify the nSample parameter calculation.

    Signed-off-by: Peter Ujfalusi
    Acked-by: Mark Brown
    Signed-off-by: Liam Girdwood

    Peter Ujfalusi
     

12 Mar, 2010

1 commit

  • Platform data option for the codec to keep the BCLK clock
    continuously running in FIFO modes (codec master).

    OMAP3 McBSP when in slave mode needs continuous BCLK running
    on the serial bus in order to operate correctly.

    Since in FIFO mode the DAC33 can also shut down the BCLK clock
    and enable it only when it is needed, let the platforms decide
    if the CPU side needs the BCLK running or not.

    Signed-off-by: Peter Ujfalusi
    Acked-by: Liam Girdwood
    Signed-off-by: Mark Brown

    Peter Ujfalusi
     

20 Jan, 2010

1 commit

  • Add possibility to configure the burst mode BCLK divider through platform
    data structure.
    The BCLK divider changes the actual speed of the serial bus in burst mode,
    which is faster than the sampling frequency of the running stream.
    In this way platforms can experiment with the optimal burst speed without
    the need to modify the codec driver itself.

    Signed-off-by: Peter Ujfalusi
    Acked-by: Liam Girdwood
    Signed-off-by: Mark Brown

    Peter Ujfalusi
     

15 Oct, 2009

1 commit

  • Driver for Texas Instruments TLV320DAC33 (SLAS546) low power stereo
    audio DAC.

    TLV320DAC33 is a stereo audio codec with integrated 24KB FIFO for low
    power audio playback.

    The digital interface can use I2S, DSP (A or B), Right and Left
    justified formats.
    DAC33 has stereo analog input, which can be bypassed to the analog
    outputs.

    Regarding to the internal 24KB FIFO the driver implements 'FIFO bypass'
    mode (default) and nSample mode (FIFO is in use).
    a) In 'FIFO bypass' mode the internal FIFO is not in use, the codec is
    working synchronously as a normal codec (it needs constant stream of
    data on the digital interface).

    b) The nSample mode implementation uses one interrupt line from DAC33 to
    the host:
    Alarm threshold is set to 10ms of audio data (limit by the driver
    implementation).
    DAC33 will signal an interrupt, when the FIFO level goes under the
    Alarm threshold.
    The host will write to nSample register a value (number of stereo
    samples), to tell DAC33 how many samples it should read in a burst from
    the host. When the DAC33 received the number of samples, it disables the
    clocks on the I2S bus. When the FIFO use again goes under the Alarm
    threshold, DAC33 signals the host with an interrupt, and the process is
    repeated.

    Signed-off-by: Peter Ujfalusi
    Signed-off-by: Mark Brown

    Peter Ujfalusi