Eric Lee / smarc-fsl-linux-kernel

13 Dec, 2011

1 commit

10 Nov, 2011

1 commit

01 Nov, 2011

1 commit

31 Aug, 2011

2 commits

15 Aug, 2011

2 commits

14 Jun, 2011

1 commit

13 Jun, 2011

1 commit

08 Jun, 2011

1 commit

  • ffdaa48ae   ASoC: Suppress restore of default register values for rbtree cache sync ... Browse Code »

    Currently the rbtree code will write out the entire register map when
    doing a cache sync which is wasteful and will slow things down. Check
    to see if the value we're about to write is the default and don't bother
    restoring it if it is, either the value will have been retained or the
    device will have been reset and holds the value already.

    We should really store the defaults in the nodes but this resolves the
    immediate issue.

    Signed-off-by: Mark Brown
    Acked-by: Liam Girdwood

    Mark Brown
     

07 Jun, 2011

2 commits

30 May, 2011

1 commit

27 May, 2011

3 commits

24 May, 2011

1 commit

20 May, 2011

2 commits

  • 7e146b558   ASoC: soc-cache: Cache a pointer to the last accessed rbnode ... Browse Code »

    Whenever we are doing a read or a write through the rbtree code, we'll
    cache a pointer to the rbnode. To avoid looking up the register
    everytime we do a read or a write, we first check if it can be found in
    the cached register block, otherwise we traverse the rbtree and finally
    cache the rbnode for future use.

    Signed-off-by: Dimitris Papastamos
    Acked-by: Liam Girdwood
    Signed-off-by: Mark Brown

    Dimitris Papastamos
     
  • 0944cc392   ASoC: soc-cache: Block based rbtree compression ... Browse Code »

    This patch prepares the ground for the actual rbtree optimization patch
    which will save a pointer to the last accessed rbnode that was used
    in either the read() or write() functions.

    Each rbnode manages a variable length block of registers. There can be no
    two nodes with overlapping blocks. Each block has a base register and a
    currently top register, all the other registers, if any, lie in between these
    two and in ascending order.

    The reasoning behind the construction of this rbtree is simple. In the
    snd_soc_rbtree_cache_init() function, we iterate over the register defaults
    provided by the driver. For each register value that is non-zero we
    insert it in the rbtree. In order to determine in which rbnode we need
    to add the register, we first look if there is another register already
    added that is adjacent to the one we are about to add. If that is the case
    we append it in that rbnode block, otherwise we create a new rbnode
    with a single register in its block and add it to the tree.

    In the next patch, where a cached rbnode is used by both the write() and the
    read() functions, we also check if the register we are about to add is in the
    cached rbnode (the least recently accessed one) and if so we append it in that
    rbnode block.

    Signed-off-by: Dimitris Papastamos
    Acked-by: Liam Girdwood
    Signed-off-by: Mark Brown

    Dimitris Papastamos
     

15 May, 2011

1 commit

  • f7391fce6   ASoC: Reintroduce do_spi_write() ... Browse Code »

    There is an unfortunate difference in return values between spi_write()
    and i2c_master_send() so we need an adaptor function to translate.

    Reported-by: Lars-Peter Clausen
    Signed-off-by: Mark Brown
    Acked-by: Liam Girdwood

    Mark Brown
     

11 May, 2011

3 commits

  • 6e28f976e   ASoC: Use spi_write() for SPI writes ... Browse Code »

    do_spi_write() is just an open coded copy of do_spi_write() so we can
    delete it and just call spi_write() directly. Indeed, as a result of
    recent refactoring all the SPI write functions are just very long
    wrappers around spi_write() which don't add anything except for some
    pointless copies so we can just use spi_write() as the hw_write
    operation directly. It should be as type safe to do this as it is to do
    the same thing with I2C and it saves us a bunch of code.

    Signed-off-by: Mark Brown
    Acked-by: Liam Girdwood

    Mark Brown
     
  • 063b7cc43   ASoC: Remove byte swap in 4x12 SPI write ... Browse Code »

    snd_soc_4_12_spi_write() contains a byte swap. Since this code was written
    for an Analog CODEC on a Blackfin reference board it appears that this is
    done because while Blackfin is little endian the CODEC is big endian (as
    are most CODECs).

    Push this up into the generic 4x12 write function and use cpu_to_be16() to
    do the byte swap so things are more regular and things work on both CPU
    endiannesses.

    Signed-off-by: Mark Brown
    Acked-by: Liam Girdwood

    Mark Brown
     
  • 051e994e9   ASoC: Don't squash 16x8 registers down to 8 bits ... Browse Code »

    Currently we'll force all registers to fit in 8 bits before passing
    down to the I/O function. Looks like a cut'n'paste bug.

    Signed-off-by: Mark Brown
    Acked-by: Liam Girdwood

    Mark Brown
     

08 May, 2011

1 commit

20 Apr, 2011

1 commit

05 Apr, 2011

3 commits

31 Mar, 2011

2 commits

27 Mar, 2011

7 commits

08 Feb, 2011

1 commit

  • 46fdaa3be   ASoC: soc-cache: dereferencing before checking ... Browse Code »

    The patch c358e640a66 "ASoC: soc-cache: Add trace event for
    snd_soc_cache_sync()" introduced a dereference of "codec->cache_ops"
    before we had checked it for NULL.

    I pulled the check forward, and then pulled everything in an indent
    level.

    Signed-off-by: Dan Carpenter
    Acked-by: Liam Girdwood
    Signed-off-by: Mark Brown

    Dan Carpenter
     

22 Jan, 2011

1 commit

20 Jan, 2011

1 commit