01 Apr, 2020
1 commit
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… drm-intel-next-fixes
gvt-next-fixes-2020-03-31
- Fix non-privilege access warning (Tina)
- Fix display port type (Tina)
- BDW cmd parser missed SWTESS_BASE_ADDRESS (Yan)
- Bypass length check of LRI (Yan)
- Fix one klocwork warning (Tina)Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200331070025.GB16629@zhen-hp.sh.intel.com
27 Mar, 2020
8 commits
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Add llu suffix and cast operator to fix the klocwork warning about
"Operands in a bitwise operation have different size"Signed-off-by: Tina Zhang
Acked-by: Zhenyu Wang
Signed-off-by: Zhenyu Wang
Link: http://patchwork.freedesktop.org/patch/msgid/20200324123021.15831-1-tina.zhang@intel.com -
This patch fixes the private_flags of mode to be checked and
compared against uapi.mode and not from hw.mode. This helps
properly trigger modeset at boot if desired by driver.It helps resolve audio_codec initialization issues if display
is connected at boot. Initial discussion on this issue has happened
on below thread:
https://patchwork.freedesktop.org/series/74828/v2: No functional change. Fixed the Closes tag and added
Maarten's RB.v3: Added Fixes tag.
Cc: Ville Syrjä
Cc: Maarten Lankhorst
Cc: Kai Vehmanen
Cc: Souza, Jose
Fixes: 58d124ea2739 ("drm/i915: Complete crtc hw/uapi split, v6.")
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1363
Suggested-by: Ville Syrjä
Signed-off-by: Uma Shankar
Signed-off-by: SweeAun Khor
Reviewed-by: Maarten Lankhorst
Link: https://patchwork.freedesktop.org/patch/msgid/20200326125111.11081-1-uma.shankar@intel.com
(cherry picked from commit d5e56705927e00f703b2eb5a98299dd6622d16e5)
Signed-off-by: Rodrigo Vivi -
We move the virtual breadcrumb from one physical engine to the next, if
the next virtual request is scheduled on a new physical engine. Since
the virtual context can only be in one signal queue, we need it to track
the current physical engine for the new breadcrumbs. However, to move
the list we need both breadcrumb locks -- and since we cannot take both
at the same time (unless we are careful and always ensure consistent
ordering) stage the movement of the signaler via the current virtual
request.Closes: https://gitlab.freedesktop.org/drm/intel/issues/1510
Fixes: 6d06779e8672 ("drm/i915: Load balancing across a virtual engine")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
Link: https://patchwork.freedesktop.org/patch/msgid/20200325130059.30600-1-chris@chris-wilson.co.uk
(cherry picked from commit 6c81e21a4742385c00713137c6fdcade0412e93c)
Signed-off-by: Rodrigo Vivi -
On Ivybridge, we can go lower than rc6 to rc6p. And this is required for
Ivybridge to hit the same minimum power consumption as rc6 on other
platforms, so make it so.v2: Update selftest to include all rc6 residency counters
Note that Andi did mention that we should be converting the magic
numbers into opaque magic macros, so if they ever get reused (unlikely
given only Ivybridge used the extra modes) we'll need to pay back the
technical debt.Closes: https://gitlab.freedesktop.org/drm/intel/issues/1518
Fixes: 730eaeb52426 ("drm/i915/gt: Manual rc6 entry upon parking")
Testcase: igt/i915_pm_rc6_residency/rc6-idle
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Cc: Mika Kuoppala
Cc: Imre Deak
Reviewed-by: Andi Shyti
Link: https://patchwork.freedesktop.org/patch/msgid/20200324134232.8773-1-chris@chris-wilson.co.uk
(cherry picked from commit 13c5a577b342d80ea06b7300ce69420a2d0928ca)
Signed-off-by: Rodrigo Vivi -
Abuse^W Take advantage that we know we are inside the GT wakeref and
that prevents any client execbuf from reopening the i915_vma in order to
claim all the vma to close without having to drop the spinlock to free
each one individually. By keeping the spinlock, we do not have to
restart if we run concurrently with i915_gem_free_objects -- which
causes them both to restart continually and make very very slow
progress.Closes: https://gitlab.freedesktop.org/drm/intel/issues/1361
Fixes: 77853186e547 ("drm/i915: Claim vma while under closed_lock in i915_vma_parked()")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
Link: https://patchwork.freedesktop.org/patch/msgid/20200323092841.22240-2-chris@chris-wilson.co.uk
(cherry picked from commit 3447c4c55d0edc95742fdcd91c3efb050546b907)
Signed-off-by: Rodrigo Vivi -
If we park/unpark faster than we can respond to RPS events, we never
will process a downclock event after expiring a waitboost, and thus we
will forever restart the GPU at max clocks even if the workload switches
and doesn't justify full power.Closes: https://gitlab.freedesktop.org/drm/intel/issues/1500
Fixes: 3e7abf814193 ("drm/i915: Extract GT render power state management")
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Cc: Lyude Paul
Reviewed-by: Andi Shyti
Link: https://patchwork.freedesktop.org/patch/msgid/20200322163225.28791-1-chris@chris-wilson.co.uk
Cc: # v5.5+
(cherry picked from commit 21abf0bf168dffff1192e0f072af1dc74ae1ff0e)
Signed-off-by: Rodrigo Vivi -
Use the restored ability to check if a context is closed to decide
whether or not to immediately ban the context from further execution
after a hang.Fixes: be90e344836a ("drm/i915/gt: Cancel banned contexts after GT reset")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
Link: https://patchwork.freedesktop.org/patch/msgid/20200319170707.8262-2-chris@chris-wilson.co.uk
(cherry picked from commit 8e37d699139128139c0468e005c2f0d6215b0c55)
Signed-off-by: Rodrigo Vivi -
I need to keep the GEM context around a bit longer so adding an explicit
flag for syncing execbuf with closed/abandonded contexts.v2:
* Use already available context flags. (Chris)Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link: https://patchwork.freedesktop.org/patch/msgid/20200319170707.8262-1-chris@chris-wilson.co.uk
(cherry picked from commit 207e4a71fb53e761be72daaeb78a49225bc31c69)
Signed-off-by: Rodrigo Vivi
20 Mar, 2020
5 commits
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On running several back to back perf capture sessions involving closing
and opening the perf stream, invalid OA reports are seen in the
beginning of the OA buffer in some sessions. Fix this by invalidating OA
TLB when the perf stream is closed or disabled on gen12.Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
Signed-off-by: Lionel Landwerlin
Link: https://patchwork.freedesktop.org/patch/msgid/20200309211057.38575-1-umesh.nerlige.ramappa@intel.com
(cherry picked from commit a639b0c15065df930467695b76ef38d5edaed049)
Signed-off-by: Rodrigo Vivi -
Beware that the context may already be closed as we try to lookup an
engine.Closes: https://gitlab.freedesktop.org/drm/intel/issues/1389
Fixes: 130a95e9098e ("drm/i915/gem: Consolidate ctx->engines[] release")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Reviewed-by: Tvrtko Ursulin
Link: https://patchwork.freedesktop.org/patch/msgid/20200316161447.18410-1-chris@chris-wilson.co.uk
(cherry picked from commit a22f34783476a39d157b60485285aaa43554cb2d)
Signed-off-by: Rodrigo Vivi -
The residual w/a batch is causing system instablity on Ivybridge and
Baytrail under some workloads, so disable until resolved.Closes: https://gitlab.freedesktop.org/drm/intel/issues/1405
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Prathap Kumar Valsan
Cc: Akeem G Abodunrin
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Acked-by: Mika Kuoppala
Reviewed-by: Rodrigo Vivi
Link: https://patchwork.freedesktop.org/patch/msgid/20200311103640.26572-1-chris@chris-wilson.co.uk
(cherry picked from commit a62774782b994026ac3198bf115717d55d536166)
Signed-off-by: Rodrigo Vivi -
Mediatek DRM Next for Linux 5.7
This include MT8183 DPI support.
Signed-off-by: Dave Airlie
From: CK Hu
Link: https://patchwork.freedesktop.org/patch/msgid/1584580683.29614.5.camel@mtksdaap41 -
amd-drm-next-5.7-2020-03-19:
amdgpu:
- SR-IOV fixes
- RAS fixes
- Fallthrough cleanups
- Kconfig fix for ACP
- Fix load balancing with VCN
- DC fixes
- GPU reset fixes
- Various cleanupsscheduler:
- Revert job distribution optimization
- Add a helper to pick the least loaded schedulerSigned-off-by: Dave Airlie
From: Alex Deucher
Link: https://patchwork.freedesktop.org/patch/msgid/20200319175418.4237-1-alexander.deucher@amd.com
19 Mar, 2020
26 commits
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There are spelling mistakes in pr_err messages and a comment. Fix these.
Signed-off-by: Colin Ian King
Signed-off-by: Alex Deucher -
clang warns:
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:754:6: warning: variable 'shadow'
is used uninitialized whenever 'if' condition is
false [-Wsometimes-uninitialized]
if (offset == grbm_cntl || offset == grbm_idx)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:757:6: note: uninitialized use
occurs here
if (shadow) {
^~~~~~
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:754:2: note: remove the 'if' if
its condition is always true
if (offset == grbm_cntl || offset == grbm_idx)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:738:13: note: initialize the
variable 'shadow' to silence this warning
bool shadow;
^
= 0
1 warning generated.shadow is only assigned in one condition and used as the condition for
another if statement; combine the two if statements and remove shadow
to make the code cleaner and resolve this warning.Fixes: 2e0cc4d48b91 ("drm/amdgpu: revise RLCG access path")
Link: https://github.com/ClangBuiltLinux/linux/issues/936
Suggested-by: Joe Perches
Reviewed-by: Nick Desaulniers
Signed-off-by: Nathan Chancellor
Signed-off-by: Alex Deucher -
fix typo for vcn2.5/jpeg2.5 idle check
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher -
fix typo for vcn2/jpeg2 idle check
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher -
fix typo for vcn1 idle check
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher -
The CAP fw is for enabling driver compatibility. Currently, it only
enabled for vega10 VF.Signed-off-by: Zhigang Luo
Reviewed-by: Shaoyun Liu
Signed-off-by: Alex Deucher -
issue smu cmd to disable all features upon baco entry for arcturus
to mitigate potential dirty I2C controller on boot
Reviewed-by: Alex Deucher
Signed-off-by: John Clements
Signed-off-by: Alex Deucher -
Originally, only the PTE valid is taken in consider.
The PRT case is missied when bo update which raise problem.
We need add condition for PRT case.v2: add PRT condition for amdgpu_vm_bo_update_mapping, too
v3: fix one typo errorSigned-off-by: Yintian Tao
Reviewed-by: Christian König
Signed-off-by: Alex Deucher -
Adds logic that will determine if pipes need merging during validation.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Chris Park
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[Why]
The scratch space can be used to pass data between x86 and DMCUB. DMCUB
will manage the actually mapping of CW7 internally, driver does not
program the window.[How]
Allocate extra space within the DMUB service's framebuffer for this
scratch space and expose them from the service for use in DC.Signed-off-by: Wyatt Wood
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[Why]
before update dpp DTO, we check dppclks in context to determine it is
changed or not, but dppclks in context will be updated anyways after
flip is done, so compare dppclks in context will always get an equal
result.[How]
Add pipe dpp clks in dccg and compare values between dccg and context.Signed-off-by: Yongqiang Sun
Reviewed-by: Dmytro Laktyushkin
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[why]
Causes regression with MST DSC displays not lighting up after DPMS[how]
Revert commit 8cc426d79be1c3 ("drm/amd/display: Program DSC during timing programming")Signed-off-by: Nikola Cornij
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[Why]
underflow happened when playing video on 1366x768 + 4K clone mode due to
incorrect handle watermark change flag and lower down clocks to early.[How]
Check watermark change flag when decide doing optimized, and check
optimized required flag to do clock update.Signed-off-by: Yongqiang Sun
Reviewed-by: Eric Yang
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[why]
this register not exist in some asic, based on request remove this from
dc.[how]
add guard for sanization.Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[Why]
We should check MST BU support capability on output port before building
vsc info packet.[How]
Add a new definition for port and sink capability check.Signed-off-by: Martin Tsai
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[WHY]
In headless boot cases, self refresh control registers are not
programmed on boot. In certain hybrid graphics cases this may cause
cstate entering to get blocked causing a hang.[HOW]
Program self refresh control register on boot.Signed-off-by: Sung Lee
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[why]
DP doesn't have message id as the first byte of an hdcp message,
current hdcp psp unifies HDMI and DP message so that it is required
when reading DP HDCP messages in hdcp_ddc, a message id needs to be
added as the first byte of the HDCP message.
The id is currently assigned as a magic number which is not a good
coding practice.[how]
Replace magic numbers with macro defined in hdcp headers.Signed-off-by: Wenjing Liu
Reviewed-by: Ashley Thomas
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[Why]
We want to be able to enable/disable psr on dmcub and fallback to dmcu
when necessary.[How]
Use dc config option to do so.Signed-off-by: Wyatt Wood
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[Why]
The default value for disable_dmcu is true, even for asics that require
dmcu.[How]
Set flag properly per asic.Signed-off-by: Wyatt Wood
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[Why]
The PSR enablement was dependent on swizzle as a workaround for
non-pageflipping fb console. It's no longer required.[How]
Remove PSR-enable dependency on swizzle mode.Signed-off-by: Roman Li
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[Why]
This is enabled by default on Renoir but there's userspace/API support
to actually make use of this.Since we're not passing this down through surface updates, let's
explicitly disable this for now.This fixes "dcn20_program_front_end_for_ctx" warnings associated with
incorrect/unexpected programming sequences performed while this is
enabled.[How]
Disable it at the topmost level in DM in case anyone tries to flip this
to enabled for any of the other ASICs like Navi10/14.Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Hersen Wu
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[Why]
A "dcn20_program_front_end_for_ctx" warning is observed on Renoir.Since the resource definition doesn't explicitly disable triplebuffer
flips like Navi10 DC actually attempts to go and setup triplebuffering
even when we pass in false to the plane state.If we hit a full update after triplebuffering has been setup we see the
assertion since we don't expect full updates while performing
triplebuffer flips.Normally this would get reset back to false whne we pass in the new
plane state, but since we never actually copy the flag when doing
surface updates this doesn't happen.[How]
Copy the flag onto the plane update based on the requested surface
update state.Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Hersen Wu
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
Right now only stream count is used to avoid split. This change updates
the W/A to check plane count instead.Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Wesley Chalmers
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[Why]
When hotplug a HDMI monitor during entering S0i3 or DPMSOFF state due to
entering infinite loop when calling vbios to program pixel clocks. In
this scenario, pll is enabled but phy is not, and there is not a
programing guide for this case.[How]
Before we having the proper programing guide, before disable pll, doing
a phy enable and disable to avoid the issue.Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[Why]
Due to previous code changes displays which are in active state
immediately transition to the active and added state. This makes the two
states redundant and unnecessary.[How]
Instead of updating the device state to active and added after
successful addition, change state to inactive if addition failed. Also,
change references to active and added state to just added state.Signed-off-by: Isabel Zhang
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher -
[why]
When reprogram MSA with updated color space, the test color space shows
inconsistency. Linux has separate routine to set up test pattern color
space, but it fails to configure RGB.[How]
Add RGB to test pattern.Fixes: 43563bc2e6a769 ("drm/amd/display: update MSA and VSC SDP on video test pattern request")
Signed-off-by: Jerry (Fangzhi) Zuo
Reviewed-by: Hersen Wu
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher
