11 Jun, 2019
1 commit
-
Linux 5.2-rc4
31 May, 2019
1 commit
-
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms and conditions of the gnu general public license
version 2 as published by the free software foundation this program
is distributed in the hope it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details you should have received a copy of the gnu general
public license along with this program if not see http www gnu org
licensesextracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 228 file(s).
Signed-off-by: Thomas Gleixner
Reviewed-by: Allison Randal
Reviewed-by: Steve Winslow
Reviewed-by: Richard Fontana
Reviewed-by: Alexios Zavras
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de
Signed-off-by: Greg Kroah-Hartman
23 May, 2019
1 commit
-
This patch sets master cleanup and also invokes tegra spi clean on
tegra spi probe failure to release tegra spi client data.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown
15 May, 2019
4 commits
-
Tegra SPI master controller has programmable trimmers to adjust the
data with respect to the clock.These trimmers are programmed in TX_CLK_TAP_DELAY and RX_CLK_TAP_DELAY
fields of COMMAND2 register.SPI TX trimmer is to adjust the outgoing data with respect to the
outgoing clock and SPI RX trimmer is to adjust the loopback clock with
respect to the incoming data from the slave device.These trimmers vary based on trace lengths of the platform design for
each of the slaves on the SPI bus and optimal value programmed is from
the platform validation across PVT.This patch adds support for configuring TX and RX clock delay trimmers
through the device tree properties.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
This patch implements set_cs_timing SPI controller method to allow
SPI client driver to configure device specific SPI CS timings.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
Tegra SPI controller supports both HW and SW based CS control
for SPI transfers.This patch adds support for HW based CS control where CS is driven
to active state during the transfer and is driven inactive at the
end of the transfer directly by the HW.This patch enables the use of HW based CS only for single transfers
without cs_change request.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
This patch adds support for GPIO based CS control through SPI core
function spi_set_cs.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown
02 May, 2019
2 commits
-
This patch fixes PIO mode transfer to use PIO bit in SPI_COMMAND1 register.
Current driver uses DMA_EN instead of PIO bit.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown
08 Apr, 2019
3 commits
-
This patch creates tegra_spi_soc_data structure to maintain and implement
SPI HW feature differences between different Tegra chips and also creates
a separate compatible string for T124/T210.Tegra210 and later has a separate interrupt mask register SPI_INTR_MASK
for enabling or disabling interrupts while Tegra124 and prior uses
interrupt enable bits in SPI_DMA_CTL register.This patch creates flag has_intr_mask_reg in tegra_spi_soc_data to
identify this and implements accordingly.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
This patch adds 3 wire transfer support to SPI mode list along with
its implementation.3 wire or Bi-directional mode uses only one serial data pin for the
transfer. SPI in master mode uses MOSI data line only and MISO data
line is not used.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
This patch adds support for dual mode SPI transfer.
Dual mode uses both MOSI and MISO lines in parallel where the data
is interleaved on MOSI and MISO lines increasing the throughput.Packet from Tx FIFO is transmitted on both MOSI and MISO lines and
packet to Rx FIFO is received from both MOSI and MISO lines. Even
bits are transmitted or received on the MOSI data line and odd bits
are transmitted or received on the MISO data line.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown
05 Apr, 2019
7 commits
-
This patch sets SPI device id from the device tree as the bus number.
Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
Packed mode expects minimum transfer length of 4 bytes.
This patch fixes this by using unpacked mode for transfers less
than 4 bytes.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
Tegra SPI supports 4 through 32 bits per word.
This patch sets bits_per_word_mask accordingly to support transfer
with these bits per word.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
This patch dumps SPI registers on transfer error or timeout for debug
purpose.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
This patch moves SPI controller reset out of spin lock.
Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
With SW CS, during the transfer completion CS is de-asserted by writing
default command1 register value to SPI_COMMAND1 register. With this both
mode and CS state are set at the same time and if current transfer mode
is different to default SPI mode and if mode change happens prior to CS
de-assert, clock polarity can change while CS is active before transfer
finishes.This causes Slave to see spurious clock edges resulting in data mismatch.
This patch fixes this by de-asserting CS before writing SPI_COMMAND1 to
its default value so through out the transfer it will be in same SPI mode.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown
01 Apr, 2019
8 commits
-
Tegra SPI controller supports lsb first mode. Default is MSB bit first
and on selection of SPI_LSB_FIRST through SPI mode transmission happens
with LSB bit first.This patch adds SPI_LSB_FIRST flag to mode_bits and also configures it
on request.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
Fixes: Use packed mode for 32 bits per word transfers to increase
performance as each packet is a full 32-bit word.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
Fixes: SPI driver can be built as module so perform SPI controller reset
on probe to make sure it is in valid state before initiating transfer.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
Fixes: Configure DMA burst size to be same as SPI TX/RX trigger levels
to avoid mismatch.SPI FIFO trigger levels are calculated based on the transfer length.
So this patch moves DMA slave configuration to happen before start
of DMAs.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
Fixes: Flush TX and RX FIFOs before start of new transfer and on FIFO
overflow or underrun errors.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
Fixes: terminate DMA and perform controller reset on transfer timeout
to clear the FIFO's and errors.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
Fixes: computation of actual bytes to fill/receive in/from FIFO in unpacked
mode when transfer length is not a multiple of requested bits per word.unpacked mode transfers fails when the transfer includes partial bytes in
the last word.Total words to be written/read to/from FIFO is computed based on transfer
length and bits per word. Unpacked mode includes 0 padding bytes for partial
words to align with bits per word and these extra bytes are also accounted
for calculating bytes left to transfer in the current driver.This causes extra bytes access of tx/rx buffers along with buffer index
position crossing actual length where remain_len becomes negative and due to
unsigned type, negative value is a 32 bit representation of signed value
and transferred bytes never meets the actual transfer length resulting in
transfer timeout and a hang.This patch fixes this with proper computation of the actual bytes to fill in
FIFO during transmit and the actual bytes to read from FIFO during receive
ignoring 0 padded bytes.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown -
Fixes: Clear packed bit when not using packed mode.
Packed bit is not cleared when not using packed mode. This results
in transfer timeouts for the unpacked mode transfers followed by the
packed mode transfers.Signed-off-by: Sowjanya Komatineni
Signed-off-by: Mark Brown
09 Oct, 2017
1 commit
-
According to "Tegra K1 Processor Technical Reference Manual" (p. 2448),
bit 20 of SPI_COMMAND1 is called CS_SW_VAL and not CS_SS_VAL.Signed-off-by: Ralf Ramsauer
Signed-off-by: Mark Brown
20 Jul, 2017
1 commit
-
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.No functional changes.
Cc: Laxman Dewangan
Cc: Mark Brown
Cc: Thierry Reding
Cc: Jonathan Hunter
Cc: linux-spi@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Philipp Zabel
Signed-off-by: Mark Brown
25 Apr, 2017
1 commit
-
trivial fix to spelling mistake in dbg_err messages
Signed-off-by: Colin Ian King
Signed-off-by: Mark Brown
20 Oct, 2014
1 commit
-
A platform_driver does not need to set an owner, it will be populated by the
driver core.Signed-off-by: Wolfram Sang
04 Sep, 2014
1 commit
-
Fix the following checkpatch warnings.
WARNING: Missing a blank line after declarations
Signed-off-by: Jingoo Han
Signed-off-by: Mark Brown
08 May, 2014
1 commit
-
Make of_device_id array const, because all OF functions
handle it as const.Signed-off-by: Jingoo Han
Acked-by: Laxman Dewangan
Signed-off-by: Mark Brown
30 Mar, 2014
3 commits
-
…ic/ti-qspi', 'spi/topic/ti-ssp', 'spi/topic/topcliff-pch', 'spi/topic/txx9', 'spi/topic/xcomm' and 'spi/topic/xfer' into spi-next
-
…512x-psc', 'spi/topic/mpc52xx', 'spi/topic/mxs', 'spi/topic/nuc900', 'spi/topic/oc-tiny' and 'spi/topic/octeon' into spi-next
-
…pic/clps711x', 'spi/topic/coldfire', 'spi/topic/completion' and 'spi/topic/davinci' into spi-next
16 Feb, 2014
1 commit
-
The purpose of commit 1e8a52e18cfb
"spi: By default setup spi_masters with 1 chipselect and dynamics bus number"
is to avoid setting default value for bus_num and num_chipselect in spi master
drivers. So let's remove the duplicate code.Signed-off-by: Axel Lin
Acked-by: Uwe Kleine-König
Acked-By: David Daney
Acked-by: Stephen Warren
Signed-off-by: Mark Brown
13 Feb, 2014
1 commit
-
In spi_add_device(), we have the code to validate spi->chip_select.
So remove the duplicate code in various drivers.Signed-off-by: Axel Lin
Acked-by: Stephen Warren
Signed-off-by: Mark Brown
11 Feb, 2014
1 commit
-
Use master->max_speed_hz instead of tspi->spi_max_frequency, so spi core will
handle checking transfer speed.In additional, since commit 052eb2d49006 'spi: core: Set max_speed_hz of
spi_device default to max_speed_hz of controller',
spi core will also set default spi->max_speed_hz if it is not set.
So remove the duplicate code in tegra_spi_setup.Signed-off-by: Axel Lin
Acked-by: Stephen Warren
Signed-off-by: Mark Brown
03 Feb, 2014
1 commit
-
For better readability, and then we can remove the comment for last transfer.
Signed-off-by: Axel Lin
Signed-off-by: Mark Brown