27 Jul, 2011
6 commits
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After changing all consumers of atomics to include , we
ran into some compile time errors due to this dependency chain:linux/atomic.h
-> asm/atomic.h
-> asm-generic/atomic-long.hwhere atomic-long.h could use funcs defined later in linux/atomic.h
without a prototype. This patches moves the code that includes
asm-generic/atomic*.h to linux/atomic.h.Archs that need need to select
CONFIG_GENERIC_ATOMIC64 from now on (some of them used to include it
unconditionally).Compile tested on i386 and x86_64 with allnoconfig.
Signed-off-by: Arun Sharma
Cc: Eric Dumazet
Cc: Ingo Molnar
Cc: David Miller
Acked-by: Mike Frysinger
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
This is in preparation for more generic atomic primitives based on
__atomic_add_unless.Signed-off-by: Arun Sharma
Signed-off-by: Hans-Christian Egtvedt
Reviewed-by: Eric Dumazet
Cc: Ingo Molnar
Cc: David Miller
Acked-by: Mike Frysinger
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
This allows us to move duplicated code in
(atomic_inc_not_zero() for now) toSigned-off-by: Arun Sharma
Reviewed-by: Eric Dumazet
Cc: Ingo Molnar
Cc: David Miller
Cc: Eric Dumazet
Acked-by: Mike Frysinger
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
The majority of architectures implement ext2 atomic bitops as
test_and_{set,clear}_bit() without spinlock.This adds this type of generic implementation in ext2-atomic-setbit.h and
use it wherever possible.Signed-off-by: Akinobu Mita
Suggested-by: Andreas Dilger
Suggested-by: Arnd Bergmann
Acked-by: Arnd Bergmann
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
[ poleg@redhat.com: no need to declare show_regs() in ptrace.h, sched.h does this ]
Signed-off-by: Mike Frysinger
Cc: Tejun Heo
Signed-off-by: Oleg Nesterov
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
The address limit is already set in flush_old_exec() so this
set_fs(USER_DS) is redundant.Signed-off-by: Mathias Krause
Cc: Koichi Yasutake
Acked-by: David Howells
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
22 Jun, 2011
1 commit
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MN10300's asm/uaccess.h needs to #include linux/kernel.h to get might_sleep()
otherwise it fails to build on MN10300 allyesconfig. This fails in a few
places with messages like the following:In file included from security/keys/trusted.c:14:
include/linux/uaccess.h: In function '__copy_from_user_nocache':
include/linux/uaccess.h:52: error: implicit declaration of function 'might_sleep'Signed-off-by: David Howells
Signed-off-by: Linus Torvalds
29 May, 2011
1 commit
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32bit and 64bit on x86 are tested and working. The rest I have looked
at closely and I can't find any problems.setns is an easy system call to wire up. It just takes two ints so I
don't expect any weird architecture porting problems.While doing this I have noticed that we have some architectures that are
very slow to get new system calls. cris seems to be the slowest where
the last system calls wired up were preadv and pwritev. avr32 is weird
in that recvmmsg was wired up but never declared in unistd.h. frv is
behind with perf_event_open being the last syscall wired up. On h8300
the last system call wired up was epoll_wait. On m32r the last system
call wired up was fallocate. mn10300 has recvmmsg as the last system
call wired up. The rest seem to at least have syncfs wired up which was
new in the 2.6.39.v2: Most of the architecture support added by Daniel Lezcano
v3: ported to v2.6.36-rc4 by: Eric W. Biederman
v4: Moved wiring up of the system call to another patch
v5: ported to v2.6.39-rc6
v6: rebased onto parisc-next and net-next to avoid syscall conflicts.
v7: ported to Linus's latest post 2.6.39 tree.> arch/blackfin/include/asm/unistd.h | 3 ++-
> arch/blackfin/mach-common/entry.S | 1 +
Acked-by: Mike FrysingerOh - ia64 wiring looks good.
Acked-by: Tony LuckSigned-off-by: Eric W. Biederman
Signed-off-by: Linus Torvalds
31 Mar, 2011
1 commit
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Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi
25 Mar, 2011
1 commit
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* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300:
MN10300: gcc 4.6 vs am33 inline assembly
MN10300: Deprecate gdbstub
MN10300: Allow KGDB to use the MN10300 serial ports
MN10300: Emulate single stepping in KGDB on MN10300
MN10300: Generalise kernel debugger kernel halt, reboot or power off hook
KGDB: Notify GDB of machine halt, reboot or power off
MN10300: Use KGDB
MN10300: Create generic kernel debugger hooks
MN10300: Create general kernel debugger cache flushing
MN10300: Introduce a general config option for kernel debugger hooks
MN10300: The icache invalidate functions should disable the icache first
MN10300: gdbstub: Restrict single-stepping to non-preemptable non-SMP configs
24 Mar, 2011
4 commits
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minix bit operations are only used by minix filesystem and useless by
other modules. Because byte order of inode and block bitmaps is different
on each architecture like below:m68k:
big-endian 16bit indexed bitmapsh8300, microblaze, s390, sparc, m68knommu:
big-endian 32 or 64bit indexed bitmapsm32r, mips, sh, xtensa:
big-endian 32 or 64bit indexed bitmaps for big-endian mode
little-endian bitmaps for little-endian modeOthers:
little-endian bitmapsIn order to move minix bit operations from asm/bitops.h to architecture
independent code in minix filesystem, this provides two config options.CONFIG_MINIX_FS_BIG_ENDIAN_16BIT_INDEXED is only selected by m68k.
CONFIG_MINIX_FS_NATIVE_ENDIAN is selected by the architectures which use
native byte order bitmaps (h8300, microblaze, s390, sparc, m68knommu,
m32r, mips, sh, xtensa). The architectures which always use little-endian
bitmaps do not select these options.Finally, we can remove minix bit operations from asm/bitops.h for all
architectures.Signed-off-by: Akinobu Mita
Acked-by: Arnd Bergmann
Acked-by: Greg Ungerer
Cc: Geert Uytterhoeven
Cc: Roman Zippel
Cc: Andreas Schwab
Cc: Martin Schwidefsky
Cc: Heiko Carstens
Cc: Yoshinori Sato
Cc: Michal Simek
Cc: "David S. Miller"
Cc: Hirokazu Takata
Acked-by: Ralf Baechle
Acked-by: Paul Mundt
Cc: Chris Zankel
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
As the result of conversions, there are no users of ext2 non-atomic bit
operations except for ext2 filesystem itself. Now we can put them into
architecture independent code in ext2 filesystem, and remove from
asm/bitops.h for all architectures.Signed-off-by: Akinobu Mita
Cc: Jan Kara
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
Introduce little-endian bit operations to the big-endian architectures
which do not have native little-endian bit operations and the
little-endian architectures. (alpha, avr32, blackfin, cris, frv, h8300,
ia64, m32r, mips, mn10300, parisc, sh, sparc, tile, x86, xtensa)These architectures can just include generic implementation
(asm-generic/bitops/le.h).Signed-off-by: Akinobu Mita
Cc: Richard Henderson
Cc: Ivan Kokshaysky
Cc: Mikael Starvik
Cc: David Howells
Cc: Yoshinori Sato
Cc: "Luck, Tony"
Cc: Ralf Baechle
Cc: Kyle McMartin
Cc: Matthew Wilcox
Cc: Grant Grundler
Cc: Paul Mundt
Cc: Kazumoto Kojima
Cc: Hirokazu Takata
Cc: "David S. Miller"
Cc: Chris Zankel
Cc: Ingo Molnar
Cc: Thomas Gleixner
Acked-by: Hans-Christian Egtvedt
Acked-by: "H. Peter Anvin"
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
GCC 4.6 explicitly represents the MDR register. It may be accessed
via the "z" constraint. Perhaps more importantly, it tracks when
the MDR register is clobbered and uses the RETF instruction if the
incoming value is still valid.Thus it is important to (at least) clobber the MDR register in
relevant inline assembly fragments, lest RETF be used incorrectly.The only instances I could find are here. There are reads of the
MDR register in kernel/gdb-stub.c, but that's harmless. Although,
frankly, __builtin_return_address(0) might be a better thing in
those cases. Certainly MDR isn't going to contain anything else
that might be useful...Signed-off-by: Richard Henderson
Signed-off-by: David Howells
23 Mar, 2011
2 commits
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All architectures can use the common dma_addr_t typedef now. We can
remove the arch specific dma_addr_t.Signed-off-by: FUJITA Tomonori
Acked-by: Arnd Bergmann
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: "H. Peter Anvin"
Cc: Ivan Kokshaysky
Cc: Richard Henderson
Cc: Matt Turner
Cc: "Luck, Tony"
Cc: Ralf Baechle
Cc: Benjamin Herrenschmidt
Cc: Heiko Carstens
Cc: Martin Schwidefsky
Cc: Chris Metcalf
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
Add a node parameter to alloc_thread_info(), and change its name to
alloc_thread_info_node()This change is needed to allow NUMA aware kthread_create_on_cpu()
Signed-off-by: Eric Dumazet
Acked-by: David S. Miller
Reviewed-by: Andi Kleen
Acked-by: Rusty Russell
Cc: Tejun Heo
Cc: Tony Luck
Cc: Fenghua Yu
Cc: David Howells
Cc:
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
19 Mar, 2011
6 commits
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Emulate single stepping in KGDB on MN10300 by way of temporary breakpoint
insertion. These breakpoints are never actually seen by KGDB, and will overlay
KGDB's own breakpoints.The breakpoints are removed by switch_to() and reinstalled on switching back so
that if preemption occurs, the preempting task doesn't hit them (though it will
still hit KGDB's regular breakpoints). If KGDB is reentered for any reason,
then the single step breakpoint is completely erased and must be set again by
the debugger.We take advantage of the fact that KGDB will effectively halt all other CPUs
whilst this CPU is single-stepping to avoid SMP problems.If the single-stepping task is preempted and killed without KGDB being
reinvoked, then the breakpoint(s) will be cleared and KGDB will be jumped back
into.Signed-off-by: David Howells
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Create generic kernel debugger hooks in the MN10300 arch and make gdbstub use
them. This is a preparation for KGDB support.Signed-off-by: David Howells
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Create general kernel debugger cache flushing for MN10300 and get rid of the
old stuff that gdbstub was using.Signed-off-by: David Howells
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Introduce a general config option for kernel debugger hooks so that both
gdbstub and kgdb can use it and add a header file for both debuggers to use.Signed-off-by: David Howells
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No users.
Signed-off-by: Thomas Gleixner
Signed-off-by: David Howells
14 Mar, 2011
2 commits
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atomic_read() needs to ensure that it emits a load (which it can do by using
ACCESS_ONCE()).Reported-by: Peter Zijlstra
Signed-off-by: David Howells -
Using __get_user_check(x, ptr++, size) leads to double increment of pointer.
This macro uses the macro get_user directly, which itself is used in this way
(get_user(x, ptr++)) in some functions of the kernel. The patch fixes the
error.Reported-by: Tkhai Kirill
Signed-off-by: David Howells
04 Dec, 2010
1 commit
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Implement asm/syscall.h for the MN10300 arch.
Signed-off-by: David Howells
Signed-off-by: Linus Torvalds
28 Oct, 2010
15 commits
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* git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300: (44 commits)
MN10300: Save frame pointer in thread_info struct rather than global var
MN10300: Change "Matsushita" to "Panasonic".
MN10300: Create a defconfig for the ASB2364 board
MN10300: Update the ASB2303 defconfig
MN10300: ASB2364: Add support for SMSC911X and SMC911X
MN10300: ASB2364: Handle the IRQ multiplexer in the FPGA
MN10300: Generic time support
MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit support
MN10300: Map userspace atomic op regs as a vmalloc page
MN10300: And Panasonic AM34 subarch and implement SMP
MN10300: Delete idle_timestamp from irq_cpustat_t
MN10300: Make various interrupt priority settings configurable
MN10300: Optimise do_csum()
MN10300: Implement atomic ops using atomic ops unit
MN10300: Make the FPU operate in non-lazy mode under SMP
MN10300: SMP TLB flushing
MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control
MN10300: Make the use of PIDR to mark TLB entries controllable
MN10300: Rename __flush_tlb*() to local_flush_tlb*()
MN10300: AM34 erratum requires MMUCTR read and write on exception entry
... -
Christoph reported a nice splat which illustrated a race in the new stack
based kmap_atomic implementation.The problem is that we pop our stack slot before we're completely done
resetting its state -- in particular clearing the PTE (sometimes that's
CONFIG_DEBUG_HIGHMEM). If an interrupt happens before we actually clear
the PTE used for the last slot, that interrupt can reuse the slot in a
dirty state, which triggers a BUG in kmap_atomic().Fix this by introducing kmap_atomic_idx() which reports the current slot
index without actually releasing it and use that to find the PTE and delay
the _pop() until after we're completely done.Signed-off-by: Peter Zijlstra
Reported-by: Christoph Hellwig
Acked-by: Rik van Riel
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
Save the current exception frame pointer in the thread_info struct rather than
in a global variable as the latter makes SMP tricky, especially when preemption
is also enabled.This also replaces __frame with current_frame() and rearranges header file
inclusions to make it all compile.Signed-off-by: David Howells
Acked-by: Akira Takeuchi -
Add support for SMSC911X and SMC911X for the ASB2364 unit.
Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells
cc: steve.glendinning@smsc.com
cc: netdev@vger.kernel.org -
Handle the IRQ multiplexer in the FPGA by implementing a cascade interrupt
driver for it.Signed-off-by: David Howells
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Implement generic time support for MN10300.
Signed-off-by: Mark Salter
Signed-off-by: David Howells -
Use an ELF HWCAP flag to indicate to the process that the CPU provides LL/SC
equivalent atomic operations unit support in addition to BSET/BCLR.Signed-off-by: Mark Salter
Signed-off-by: David Howells -
The AM34 processor has an atomic operation that's the equivalent of LL/SC on
other architectures. However, rather than being done through a pair of
instructions, it's driven by writing to a pair of memory-mapped CPU control
registers.One set of these registers (AARU/ADRU/ASRU) is available for use by userspace,
but for userspace to access them a PTE must be set up to cover the region.
This is done by dedicating the first vmalloc region page to this purpose,
setting the permissions on its PTE such that userspace can access the page.glibc is hardcoded to expect the registers to be there.
The way atomic ops are done through these registers is straightforward:
(1) Write the address of the word you wish to access into AARU. This causes
the CPU to go and fetch that word and load it into ADRU. The status bits
are also cleared in ASRU.(2) The current data value is read from the ADRU register and modified.
(3) To alter the data in RAM, the revised data is written back to the ADRU
register, which causes the CPU to attempt to write it back.(4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch),
ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then
must be checked to confirm that the operation wasn't aborted. If any of
the watches have been set to true, the operation was aborted.Signed-off-by: Mark Salter
Signed-off-by: David Howells -
Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for
MN10300. Also implement support for the MN2WS0060 processor and the ASB2364
evaluation board which are AM34 based.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
Delete idle_timestamp from irq_cpustat_t as it's an unread relic.
Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
Make the settings of interrupt priorities used by various services configurable
at run time.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
Implement atomic ops using the atomic ops unit available in the AM34 CPU. This
allows the equivalent of the LL/SC instructions to be found on other CPUs.Signed-off-by: Mark Salter
Signed-off-by: David Howells -
Make the FPU operate in non-lazy mode under SMP so that when the process that
is currently using the FPU migrates to a different CPU, we don't have to ping
its previous CPU to flush the FPU context.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
Implement global TLB flushing for MN10300. This will be used by the AM34 which
is SMP capable.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells -
Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits
are a more suitable layout.Signed-off-by: Akira Takeuchi
Signed-off-by: Kiyoshi Owada
Signed-off-by: David Howells
