18 Jul, 2019
1 commit
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As the below diagram shows, to achieve a particular serial clock rate,
we should choose an appropriate CO divider value(1/2/4/8) so that PLL
VCO frequency(fvco) is in specified range(640MHz ~ 1500MHz).--------- 640MHz ~ 1500MHz ------------ --------------
| PLL VCO | ----------------> | CO divider | -> | serial clock |
--------- ------------ --------------
1/2/4/8 div 7 * phy_clk_rateThis patch configures CO divider to be appropriate value to meet the fvco
range requirement. This may address display flicker issue seen on some
SoC samples.Signed-off-by: Liu Ying
18 Apr, 2019
15 commits
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This is a cleaned up port of the downstream i.MX8MQ USB3 PHY driver.
Signed-off-by: Li Jun
Signed-off-by: Lucas Stach
Signed-off-by: Kishon Vijay Abraham I
(cherry picked from commit efe81bea891586680a928ea5dde40eb1fff34be2) -
Due to i.MX8 clock issue, we need to get PHY clock rate
before setting it's rate when system resumes back from
PM sleep mode, otherwise, we'll fail to set the clock rate.
So, this is a workaround and it can be removed when
the clock issue is properly fixed.Signed-off-by: Liu Ying
(cherry picked from commit fca3d4b1074fbc3ca74db040f6abdf9b614df819) -
Due to i.MX8 clock issue, we need to get PHY clock rate
before setting it's rate when system resumes back from
PM sleep mode, otherwise, we'll fail to set the clock rate.
So, this is a workaround and it can be removed when
the clock issue is properly fixed.Signed-off-by: Liu Ying
(cherry picked from commit f9709fbf36495c7139ac55a0ecc01b30303b427b) -
The reset needs to be set in phy_init to handle the warm reset case.
Signed-off-by: Oliver Brown
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Improving the PHY timing parameters by using linear interpolation for the linear parameters.
For, the non-linear parameters, use more frequency steps to improve the accuracy.Signed-off-by: Oliver Brown
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Some of the Mixel phy (the MIPI DPHY found on 8QM, 8QXP and 8M), have
different addresses, depending on the platform.Update the driver to have the correct address for a corresponding
platform.Signed-off-by: Robert Chiras
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Update the register settings for PRG values to be more accurate,
depending on the timing used.
Also, update the init function to make sure the PHY is powered OFF in
this stage, and the power_on function to correctly power ON the PHY
according to the specification: assert PD_PLL, wait for LOCK, assert
PD_DPHY.Signed-off-by: Robert Chiras
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When setting up the CM, CN and CO decimal values for DPHY PLL, these
values should only be rounded up when a "best_match" is requested. Some
DSI receivers requires the DSI clock to be exactly matched with the
pixel clock.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com -
Added compatible string for i.MX8MQ platform.
Signed-off-by: Robert Chiras
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Currently, the Northwest Logic MIPI-DSI controller host specific code
resides under drm/bridge, but is not a real drm_bridge. It creates a
drm_bridge and adds itself to the drm_encoder that handles this file,
but this is wrong, since it does not implement the drm_bridge_funcs.The correct way to implement a drm_bridge is to add the drm_bridge and
let other components (another bridge or a drm_encoder) to attach to this
bridge.
Since we are doing this, a new compatible strings can be used for this
driver: "nwl,mipi-dsi".Since this was used by nwl_dsi-imx.c, update that driver to use this
bridge correctly.This is needed in order to add support for MIPI-DSI on 8MQ. The IMX_NWL
driver will either add a DSI encoder to DRM, or a DSI bridge.
The encoder will be used by imx-drm-core driver, while the bridge
will be used by MXSFB driver (which creates a simple display pipe).Signed-off-by: Robert Chiras
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Implement the DPHY from MIPI-DSI found on i.MX8 platforms (QM, QXP and MQ)
as a phy driver.Signed-off-by: Robert Chiras
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It seems that we haven't got SCU ISO bit available to check if PHY is
locked or not after enable, so let's simply delay for a while as a
temporary solution.Signed-off-by: Liu Ying
Signed-off-by: Vipul Kumar -
It seems that we haven't got SCU ISO bit available to check if PHY is
locked or not after enable, so let's simply delay for a while as a
temporary solution.Signed-off-by: Liu Ying
Signed-off-by: Vipul Kumar -
This patch adds Mixel LVDS combo PHY support(MIPI DSI and LVDS combo).
This LVDS PHY supports one LVDS channel in single mode and two channels in
dual mode.Signed-off-by: Liu Ying
Signed-off-by: Vipul Kumar -
This patch adds Mixel LVDS PHY support.
This PHY supports two LVDS channels.Signed-off-by: Liu Ying
Signed-off-by: Vipul Kumar
03 Apr, 2019
1 commit
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commit 1396929e8a903db80425343cacca766a18ad6409 upstream.
While only the first PHY supports mode switching, the remaining PHYs
work in USB host mode. They should support set_mode with mode=USB_HOST
instead of failing. This is especially needed now that the USB core does
set_mode for all USB ports, which was added in commit b97a31348379 ("usb:
core: comply to PHY framework").Make set_mode with mode=USB_HOST a no-op instead of failing for the
non-OTG USB PHYs.Fixes: 6ba43c291961 ("phy-sun4i-usb: Add support for phy_set_mode")
Signed-off-by: Chen-Yu Tsai
Cc: stable
Signed-off-by: Greg Kroah-Hartman
06 Mar, 2019
2 commits
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[ Upstream commit 827cb0323928952c0db9515aba9d534fb1285b3f ]
I submitted this driver several times before it got accepted. The
first series hasn't been accepted but the DTS binding did made it.
I then made a second series that added generic reset support to the
PHY core, this in turn required a change to the DT binding. This
second series seemed to have been ignored, so I did a third one
without the change to the PHY core and the DT binding update, and this
last attempt finally made it.But two months later the DT binding update from the second series has
been integrated too. So now the driver doesn't match the binding and
the only DTS using it. This patch fix the driver to match the new
binding.Signed-off-by: Alban Bedel
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin -
[ Upstream commit 009808154c69c48d5b41fc8cf5ad5ab5704efd8f ]
In the power on function the error path doesn't return the suspend
override to its proper state. It should should deassert this reset
line to enable the suspend override.Signed-off-by: Alban Bedel
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin
13 Feb, 2019
1 commit
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[ Upstream commit 2659392e5c08dff626e6db1d739adff58a94604d ]
The new Allwinner H6 SoC's USB2 PHY has two holes -- USB1 (which is a
3.0 port with dedicated PHY) and USB2 (which doesn't exist at all).Add support for this kind of missing USB PHY index.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin
17 Dec, 2018
2 commits
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[ Upstream commit c88520db18ba0b9a41326c3b8680e7c09eb4c381 ]
Tune1 register on sdm845 is used to update HSTX_TRIM with fused
setting. Enable same by specifying update_tune1_with_efuse flag
for sdm845, otherwise driver ends up programming tune2 register.Fixes: ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845")
Signed-off-by: Manu Gautam
Reviewed-by: Douglas Anderson
Reviewed-by: Stephen Boyd
Acked-by: Vivek Gautam
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin -
[ Upstream commit 6e34d358b24ffc40764eb3681164c79091765429 ]
Fix HSTX_TRIM tuning logic which instead of using fused value
as HSTX_TRIM, incorrectly performs bitwise OR operation with
existing default value.Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
Signed-off-by: Manu Gautam
Reviewed-by: Douglas Anderson
Reviewed-by: Stephen Boyd
Acked-by: Vivek Gautam
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin
30 Jul, 2018
1 commit
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We want the USB fixes in here as well to handle merge issues.
Signed-off-by: Greg Kroah-Hartman
24 Jul, 2018
1 commit
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Use the appropriate SPDX license identifier and drop the license text.
This patch is only cosmetic.Signed-off-by: Antoine Tenart
Signed-off-by: Kishon Vijay Abraham I
10 Jul, 2018
7 commits
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Use the appropriate SPDX license identifier and drop the previous
license text.Signed-off-by: Jisheng Zhang
Signed-off-by: Kishon Vijay Abraham I -
This PHY is still mostly undocumented -- the only documented registers
exist on R-Car V3H (R8A77980) SoC where this PHY stays in a powered-down
state after a reset and thus we must power it up for PCIe to work...Signed-off-by: Sergei Shtylyov
Reviewed-by: Simon Horman
Signed-off-by: Kishon Vijay Abraham I -
In preparation to enabling -Wimplicit-fallthrough, mark switch cases
where we are expecting to fall through.Signed-off-by: Gustavo A. R. Silva
Signed-off-by: Kishon Vijay Abraham I -
Add Stingray PCIe PHY driver for both PAXB and PAXC root complex
Signed-off-by: Ray Jui
Signed-off-by: Kishon Vijay Abraham I -
Some platforms support BC12 which is disabled by default,
here add a property to enable it if needSigned-off-by: Chunfeng Yun
Signed-off-by: Kishon Vijay Abraham I -
Add properties for Eye diagram test of HQA which sometimes need
adjust some parameters of u2phySigned-off-by: Chunfeng Yun
Signed-off-by: Kishon Vijay Abraham I -
Use SPDX-License-Identifier tag instead of the GPL license text
Signed-off-by: Chunfeng Yun
Signed-off-by: Kishon Vijay Abraham I
29 Jun, 2018
2 commits
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Kbuilt test robot reported:
drivers/phy/motorola/phy-mapphone-mdm6600.c:188:16: warning: is used
uninitialized in this function [-Wuninitialized]
val |= values[i] << i;
~~~~~~^~~Looking at the phy_mdm6600_status() values does get initialized by
gpiod_get_array_value_cansleep(), but we are using wrong enum
in that function. Let's fix the use, both end up being three though
so urgent rush on this one AFAIK.Fixes: 5d1ebbda0318 ("phy: mapphone-mdm6600: Add USB PHY driver for
MDM6600 on Droid 4")
Reported-by: kbuild test robot
Signed-off-by: Tony Lindgren
Reviewed-by: Pavel Machek
Signed-off-by: Kishon Vijay Abraham I -
Unset is required to enable USB 3.0 PHY when XHCI reenabled in response
to setting PHY3_IDDQ_OVERRIDE in uninit().Fixes: cd6f769fdea7 ("phy: phy-brcm-usb-init: Power down USB 3.0 PHY when XHCI disabled")
Signed-off-by: Jaedon Shin
Signed-off-by: Kishon Vijay Abraham I
07 Jun, 2018
1 commit
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Pull networking updates from David Miller:
1) Add Maglev hashing scheduler to IPVS, from Inju Song.
2) Lots of new TC subsystem tests from Roman Mashak.
3) Add TCP zero copy receive and fix delayed acks and autotuning with
SO_RCVLOWAT, from Eric Dumazet.4) Add XDP_REDIRECT support to mlx5 driver, from Jesper Dangaard
Brouer.5) Add ttl inherit support to vxlan, from Hangbin Liu.
6) Properly separate ipv6 routes into their logically independant
components. fib6_info for the routing table, and fib6_nh for sets of
nexthops, which thus can be shared. From David Ahern.7) Add bpf_xdp_adjust_tail helper, which can be used to generate ICMP
messages from XDP programs. From Nikita V. Shirokov.8) Lots of long overdue cleanups to the r8169 driver, from Heiner
Kallweit.9) Add BTF ("BPF Type Format"), from Martin KaFai Lau.
10) Add traffic condition monitoring to iwlwifi, from Luca Coelho.
11) Plumb extack down into fib_rules, from Roopa Prabhu.
12) Add Flower classifier offload support to igb, from Vinicius Costa
Gomes.13) Add UDP GSO support, from Willem de Bruijn.
14) Add documentation for eBPF helpers, from Quentin Monnet.
15) Add TLS tx offload to mlx5, from Ilya Lesokhin.
16) Allow applications to be given the number of bytes available to read
on a socket via a control message returned from recvmsg(), from
Soheil Hassas Yeganeh.17) Add x86_32 eBPF JIT compiler, from Wang YanQing.
18) Add AF_XDP sockets, with zerocopy support infrastructure as well.
From Björn Töpel.19) Remove indirect load support from all of the BPF JITs and handle
these operations in the verifier by translating them into native BPF
instead. From Daniel Borkmann.20) Add GRO support to ipv6 gre tunnels, from Eran Ben Elisha.
21) Allow XDP programs to do lookups in the main kernel routing tables
for forwarding. From David Ahern.22) Allow drivers to store hardware state into an ELF section of kernel
dump vmcore files, and use it in cxgb4. From Rahul Lakkireddy.23) Various RACK and loss detection improvements in TCP, from Yuchung
Cheng.24) Add TCP SACK compression, from Eric Dumazet.
25) Add User Mode Helper support and basic bpfilter infrastructure, from
Alexei Starovoitov.26) Support ports and protocol values in RTM_GETROUTE, from Roopa
Prabhu.27) Support bulking in ->ndo_xdp_xmit() API, from Jesper Dangaard
Brouer.28) Add lots of forwarding selftests, from Petr Machata.
29) Add generic network device failover driver, from Sridhar Samudrala.
* ra.kernel.org:/pub/scm/linux/kernel/git/davem/net-next: (1959 commits)
strparser: Add __strp_unpause and use it in ktls.
rxrpc: Fix terminal retransmission connection ID to include the channel
net: hns3: Optimize PF CMDQ interrupt switching process
net: hns3: Fix for VF mailbox receiving unknown message
net: hns3: Fix for VF mailbox cannot receiving PF response
bnx2x: use the right constant
Revert "net: sched: cls: Fix offloading when ingress dev is vxlan"
net: dsa: b53: Fix for brcm tag issue in Cygnus SoC
enic: fix UDP rss bits
netdev-FAQ: clarify DaveM's position for stable backports
rtnetlink: validate attributes in do_setlink()
mlxsw: Add extack messages for port_{un, }split failures
netdevsim: Add extack error message for devlink reload
devlink: Add extack to reload and port_{un, }split operations
net: metrics: add proper netlink validation
ipmr: fix error path when ipmr_new_table fails
ip6mr: only set ip6mr_table from setsockopt when ip6mr_new_table succeeds
net: hns3: remove unused hclgevf_cfg_func_mta_filter
netfilter: provide udp*_lib_lookup for nf_tproxy
qed*: Utilize FW 8.37.2.0
...
21 May, 2018
6 commits
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Support XS-PHY for MediaTek SoCs with USB3.1 GEN2 controller
Signed-off-by: Chunfeng Yun
Signed-off-by: Kishon Vijay Abraham I -
There are two QUSB2 PHYs present on sdm845. In order
to improve eye diagram for both the PHYs some parameters
need to be changed. Provide device tree properties to
override these from board specific device tree files.Signed-off-by: Manu Gautam
Reviewed-by: Douglas Anderson
Signed-off-by: Kishon Vijay Abraham I -
QMP V3 UNI PHY is a single lane USB3 PHY without support
for DisplayPort (DP).
Main difference from DP combo QMPv3 PHY is that UNI PHY
doesn't have dual RX/TX lanes and no separate DP_COM
block for configuration related to type-c or DP.
Also remove "qcom,qmp-v3-usb3-phy" compatible string which
was earlier added for sdm845 only as there wouldn't be
any user of same.
While at it, fix has_pwrdn_delay attribute for USB-DP
PHY configuration and.Reviewed-by: Evan Green
Signed-off-by: Manu Gautam
Signed-off-by: Kishon Vijay Abraham I -
Driver currently crashes due to NULL pointer deference
while updating PHY tune register if nvmem cell is NULL.
Since, fused value for Tune1/2 register is optional,
we'd rather bail out.Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
Reviewed-by: Vivek Gautam
Reviewed-by: Evan Green
Cc: stable # 4.14+
Signed-off-by: Manu Gautam
Signed-off-by: Kishon Vijay Abraham I -
QMP PHY for USB/PCIE requires pipe_clk for locking of
retime buffers at the pipe interface. Driver checks for
PHY_STATUS without enabling pipe_clk due to which
phy_init() fails with initialization timeout.
Though pipe_clk is output from PHY (after PLL is programmed
during initialization sequence) to GCC clock_ctl and then fed
back to PHY but for PHY_STATUS register to reflect successful
initialization pipe_clk from GCC must be present.
Since, clock driver now ignores status_check for pipe_clk on
clk_enable/disable, driver can safely enable/disable pipe_clk
from phy_init/exit.Signed-off-by: Manu Gautam
Signed-off-by: Kishon Vijay Abraham I -
This patch fixes the following issues:
* warning reported by checkpatch:
WARNING: line over 80 characters
#87: FILE: drivers/phy/st/phy-stm32-usbphyc.c:87:
+static void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params *pll_params)* bug reported by static checker (Dan Carpenter):
drivers/phy/st/phy-stm32-usbphyc.c:371 stm32_usbphyc_probe()
error: uninitialized symbol 'i'.* unused stm32_usbphyc structure member: bool pll_enabled.
* unnecessary extra line in stm32_usbphyc_of_xlate
Fixes: 94c358da3a05 "phy: stm32: add support for STM32 USB PHY Controller (USBPHYC)"
Signed-off-by: Amelie Delaunay
Signed-off-by: Kishon Vijay Abraham I
