Eric Lee / smarc-fsl-linux-kernel

07 Dec, 2006

1 commit

  • 9d26e2134   [TG3]: Add TG3_FLG2_IS_NIC flag. ... Browse Code »

    Add Tg3_FLG2_IS_NIC flag to unambiguously determine whether the
    device is NIC or onboard. Previously, the EEPROM_WRITE_PROT flag was
    overloaded to also mean onboard. With the separation, we can
    support some devices that are onboard but do not use eeprom write
    protect.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     

29 Sep, 2006

6 commits

08 Aug, 2006

1 commit

  • 1b2a72050   [TG3]: Fix tx race condition ... Browse Code »

    Fix a subtle race condition between tg3_start_xmit() and tg3_tx()
    discovered by Herbert Xu :

    CPU0 CPU1
    tg3_start_xmit()
    if (tx_ring_full) {
    tx_lock
    tg3_tx()
    if (!netif_queue_stopped)
    netif_stop_queue()
    if (!tx_ring_full)
    update_tx_ring
    netif_wake_queue()
    tx_unlock
    }

    Even though tx_ring is updated before the if statement in tg3_tx() in
    program order, it can be re-ordered by the CPU as shown above. This
    scenario can cause the tx queue to be stopped forever if tg3_tx() has
    just freed up the entire tx_ring. The possibility of this happening
    should be very rare though.

    The following changes are made:

    1. Add memory barrier to fix the above race condition.

    2. Eliminate the private tx_lock altogether and rely solely on
    netif_tx_lock. This eliminates one spinlock in tg3_start_xmit()
    when the ring is full.

    3. Because of 2, use netif_tx_lock in tg3_tx() before calling
    netif_wake_queue().

    4. Change TX_BUFFS_AVAIL to an inline function with a memory barrier.
    Herbert and David suggested using the memory barrier instead of
    volatile.

    5. Check for the full wake queue condition before getting
    netif_tx_lock in tg3_tx(). This reduces the number of unnecessary
    spinlocks when the tx ring is full in a steady-state condition.

    6. Update version to 3.65.

    Signed-off-by: Michael Chan
    Acked-by: Herbert Xu
    Signed-off-by: David S. Miller

    Michael Chan
     

01 Jul, 2006

3 commits

  • 52c0fd834   [TG3]: Add TSO workaround using GSO ... Browse Code »

    Use GSO to workaround a rare TSO bug on some chips. This hardware
    bug may be triggered when the TSO header size is greater than 80
    bytes. When this condition is detected in a TSO packet, the driver
    will use GSO to segment the packet to workaround the hardware bug.

    Thanks to Juergen Kreileder for reporting the
    problem and collecting traces to help debug the problem.

    And thanks to Herbert Xu for providing
    the GSO mechanism that happens to be the perfect workaround for this
    problem.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     
  • 1661394e7   [TG3]: Turn on hw fix for ASF problems ... Browse Code »

    Clear a bit to enable a hardware fix for some ASF related problem.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     
  • f92905deb   [TG3]: Add rx BD workaround ... Browse Code »

    Add workaround to limit the burst size of rx BDs being DMA'ed to the
    chip. This works around hardware errata on a number of 5750, 5752,
    and 5755 chips.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     

18 Jun, 2006

2 commits

  • 00b705042   [TG3]: Convert to non-LLTX ... Browse Code »

    Herbert Xu pointed out that it is unsafe to call netif_tx_disable()
    from LLTX drivers because it uses dev->xmit_lock to synchronize
    whereas LLTX drivers use private locks.

    Convert tg3 to non-LLTX to fix this issue. tg3 is a lockless driver
    where hard_start_xmit and tx completion handling can run concurrently
    under normal conditions. A tx_lock is only needed to prevent
    netif_stop_queue and netif_wake_queue race condtions when the queue
    is full.

    So whether we use LLTX or non-LLTX, it makes practically no
    difference.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     
  • df3e65481   [TG3]: Add recovery logic when MMIOs are re-ordered ... Browse Code »

    Add recovery logic when we suspect that the system is re-ordering
    MMIOs. Re-ordered MMIOs to the send mailbox can cause bogus tx
    completions and hit BUG_ON() in the tx completion path.

    tg3 already has logic to handle re-ordered MMIOs by flushing the MMIOs
    that must be strictly ordered (such as the send mailbox). Determining
    when to enable the flush is currently a manual process of adding known
    chipsets to a list.

    The new code replaces the BUG_ON() in the tx completion path with the
    call to tg3_tx_recover(). It will set the TG3_FLAG_MBOX_WRITE_REORDER
    flag and reset the chip later in the workqueue to recover and start
    flushing MMIOs to the mailbox.

    A message to report the problem will be printed. We will then decide
    whether or not to add the host bridge to the list of chipsets that do
    re-ordering.

    We may add some additional code later to print the host bridge's ID so
    that the user can report it more easily.

    The assumption that re-ordering can only happen on x86 systems is also
    removed.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     

10 Jun, 2006

1 commit

  • f49639e64   [TG3]: Handle Sun onboard tg3 chips more correctly. ... Browse Code »

    Get rid of all the SUN_570X logic and instead:

    1) Make sure MEMARB_ENABLE is set when we probe the SRAM
    for config information. If that is off we will get
    timeouts.

    2) Always try to sync with the firmware, if there is no
    firmware running do not treat it as an error and instead
    just report it the first time we notice this condition.

    3) If there is no valid SRAM signature, assume the device
    is onboard by setting TG3_FLAG_EEPROM_WRITE_PROT.

    Update driver version and release date.

    With help from Michael Chan and Fabio Massimo Di Nitto.

    Signed-off-by: David S. Miller

    David S. Miller
     

30 Apr, 2006

1 commit

10 Apr, 2006

2 commits

  • bbadf503d   [TG3]: Speed up SRAM access (2nd version) ... Browse Code »

    Speed up SRAM read and write functions if possible by using MMIO
    instead of config. cycles. With this change, the post reset signature
    done at the end of D3 power change must now be moved before the D3
    power change.

    IBM reported a problem on powerpc blades during ethtool self test that
    was caused by the memory test taking excessively long. Config. cycles
    are very slow on powerpc and the memory test can take more than 10
    seconds to complete using config. cycles.

    David Miller informed me that an earlier version of the patch caused
    problems on sparc64 systems with built-in tg3 chips. This version
    fixes the problem by excluding all SUN built-in tg3 chips from doing
    MMIO SRAM access.

    TG3_FLAG_EEPROM_WRITE_PROT is also set unconditionally when
    TG3_FLG2_SUN_570X is set. This should be sane as all SUN chips are
    built-in and do not require Vaux switching.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     
  • d2d746f83   [TG3]: Kill some less useful flags ... Browse Code »

    Kill the TG3_FLAG_NO_{TX|RX}_PSEUDO_CSUM flags because they are not
    very useful. This will free up some bits for new flags.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     

23 Mar, 2006

2 commits

21 Mar, 2006

5 commits

20 Mar, 2006

1 commit

  • 4a29cc2e5   [TG3]: 40-bit DMA workaround part 2 ... Browse Code »

    The 40-bit DMA workaround recently implemented for 5714, 5715, and
    5780 needs to be expanded because there may be other tg3 devices
    behind the EPB Express to PCIX bridge in the 5780 class device.

    For example, some 4-port card or mother board designs have 5704 behind
    the 5714.

    All devices behind the EPB require the 40-bit DMA workaround.

    Thanks to Chris Elmquist again for reporting the problem and testing
    the patch.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     

03 Feb, 2006

1 commit

  • 7faa006f9   [TG3]: Flush tg3_reset_task() ... Browse Code »

    Make sure tg3_reset_task() is flushed in the close and suspend paths
    as noted by Jeff Garzik.

    In the close path, calling flush_scheduled_work() may cause deadlock
    if linkwatch_event() is on the workqueue. linkwatch_event() will try
    to get the rtnl_lock() which is already held by tg3_close(). So
    instead, we set a flag in tg3_reset_task() and tg3_close() polls
    the flag until it is cleared.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     

17 Jan, 2006

1 commit

  • ec41c7dfd   [TG3]: Refine nvram locking ... Browse Code »

    Add nvram lock count so that calls to tg3_nvram_lock()/unlock() can
    be nested. Add error checking to all callers of tg3_nvram_lock()
    where appropriate. To prevent nvram lock failures after halting the
    firmware, it is also necessary to release firmware's nvram lock in
    tg3_halt_cpu().

    Update version to 3.48.

    Based on David Miller's initial patch.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     

29 Dec, 2005

1 commit

  • 091465d75   [TG3]: ethtool -d hangs PCIe systems ... Browse Code »

    Resubmitting after recommendation to use GET_REG32_1() instead of
    GET_REG32_LOOP(..., 1). Retested. Problem remains fixed.

    Prevent tg3_get_regs() from reading reserved and undocumented registers
    at RX_CPU_BASE and TX_CPU_BASE offsets which caused hostile behavior
    on PCIe platforms.

    Acked-by: Michael Chan
    Signed-off-by: David S. Miller

    Chris Elmquist
     

14 Dec, 2005

1 commit

  • 6921d201f   [TG3]: Fix low power state ... Browse Code »

    Fix the following bugs in tg3_set_power_state():

    1. Both WOL and ASF flags require switching to aux power.

    2. Add a missing handshake with firmware to enable WOL.

    3. Turn off the PHY if both WOL and ASF are disabled.

    4. Add nvram arbitration before halting the firmware.

    5. Fix tg3_setup_copper_phy() to switch to 100Mbps when
    changing to low power state.

    Update revision and date.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     

29 Oct, 2005

2 commits

  • 28fbef78a   [PATCH] tg3: fix ASF heartbeat ... Browse Code »

    Change the ASF heart beat to 5 seconds for faster detection of system
    crash. The driver sends the heartbeat every 2 seconds and the ASF
    firmware will timeout and reset the device if no heartbeat is received
    after 5 seconds. The old scheme of 2 minutes is ineffective.

    tg3_write_mem_fast() is added to speed up the IO to send the heartbeat.
    When no workaround is needed, it will use direct MMIO to memory space
    to write to memory.

    Signed-off-by: Michael Chan
    Signed-off-by: Jeff Garzik

    Michael Chan
     
  • a4e2b3478   [PATCH] tg3: add 5714/5715 support ... Browse Code »

    Add complete support for 5714/5715. These chips are very similar to
    5780 so the changes are very trivial. A TG3_FLG2_5780_CLASS flag is
    added to identify these chips.

    Signed-off-by: Michael Chan
    Signed-off-by: Jeff Garzik

    Michael Chan
     

28 Sep, 2005

1 commit

  • c94e39418   [TG3]: 5780 PHY fixes ... Browse Code »

    Fix 5780 PHY related problems:

    1. MAC_RX_MODE reset must be done before setting up the MAC_MODE
    register on 5705_PLUS chips or the chip will stop receiving after
    a while. The MAC_RX_MODE reset is needed to prevent intermittently
    losing the first receive packet on serdes chips.

    2. Skip MAC loopback test on 5780 because of hardware errata. Normal
    traffic including PHY loopback is not affected by the errata.

    3. PHY loopback fails intermittently on 5708S and this is fixed by
    putting the PHY in loopback mode first before programming the MAC
    mode register. A MAC_RX_MODE reset is also added.

    4. Return -EINVAL in tg3_nway_reset() if device is in TBI mode. Allow
    nway_reset if 5780S is in parallel detect mode.

    5. Add missing PHY IDs in KNOWN_PHY_ID() macro.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     

30 Aug, 2005

3 commits

  • 6892914fb   [TG3]: Add indirect register method for 5703 behind ICH ... Browse Code »

    This patch adds the new workaround for 5703 A1/A2 if it is behind
    certain ICH bridges. The workaround disables memory and uses config.
    cycles only to access all registers. The 5702/03 chips can mistakenly
    decode the special cycles from the ICH chipsets as memory write cycles,
    causing corruption of register and memory space. Only certain ICH
    bridges will drive special cycles with non-zero data during the address
    phase which can fall within the 5703's address range. This is not an ICH
    bug as the PCI spec allows non-zero address during special cycles.
    However, only these ICH bridges are known to drive non-zero addresses
    during special cycles.

    The indirect_lock is also changed to spin_lock_irqsave from spin_lock_bh
    because it is used in irq handler when using the indirect method to
    disable interrupts.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     
  • 09ee929cc   [TG3]: Add mailbox read method ... Browse Code »

    This patch adds the mailbox read method and also adds an inline function
    tw32_mailbox_f() for mailbox writes that require read flush.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     
  • 200949306   [TG3]: Add basic register access function pointers ... Browse Code »

    This patch adds the basic function pointers to do register accesses in
    the fast path. This was suggested by David Miller. The idea is that
    various register access methods for different hardware errata can easily
    be implemented with these function pointers and performance will not be
    degraded on chips that use normal register access methods.

    The various register read write macros (e.g. tw32, tr32, tw32_mailbox)
    are redefined to call the function pointers.

    Signed-off-by: Michael Chan
    Signed-off-by: David S. Miller

    Michael Chan
     

26 Jul, 2005

5 commits