24 May, 2016
14 commits
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Add pinctrls for usbotg1 and usbotg2 vbus control. This missing keeps
the vbus enable pin is high after power up, so vbus is on and otg port
will not enter suspend in device mode, as active usb port has high
bus freq requested, this prevents system enter low bus freq.Signed-off-by: Li Jun
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The 'pm_runtime_get_sync()' and 'pm_runtime_put_sync_suspend()'
may be called not pairs. And this will cause the 'usage_count'
to be negative.Signed-off-by: Fancy Fang
(cherry picked from commit 10135c736dfc1b3d5c449adb78118e3642b99276) -
Add 'ipg' and 'axi' clocks for pxp which should
be used to control runtime power managments.Signed-off-by: Fancy Fang
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The pxp require two clocks to enable when it works, and
they are 'ipg' and 'axi' clocks. Besides, the two clocks
share the same CCGR to control clock gating.Signed-off-by: Fancy Fang
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missed the brackets for bch legacy support, which leads the large oob
nand bch setting to wrong path.Signed-off-by: Han Xu
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document the new option for legacy bch geometry support.
Conflicts:
Documentation/devicetree/bindings/mtd/gpmi-nand.txtSigned-off-by: Han Xu
(cherry picked from commit c1c24ecd24cb808e825eb13a3e3d016c283322cc) -
Provide an option in DT to use legacy bch geometry, which compatible
with the 3.10 kernel bch setting. To enable the feature, adding
"fsl,legacy-bch-geometry" under gpmi-nand node.NOTICE: The feature must be enabled/disabled in both u-boot and kernel.
Conflicts:
drivers/mtd/nand/gpmi-nand/gpmi-nand.hSigned-off-by: Han Xu
(cherry picked from commit 4d28b1693905526558892d40525763e6bc4469e4) -
Fix chipidea usb driver compile warning if CONFIG_USB_CHIPIDEA_HOST
is disabled:
In file included from drivers/usb/chipidea/otg.c:26:0:
drivers/usb/chipidea/host.h:23:13: warning: 'ci_hdrc_host_driver_init'
defined but not used [-Wunused-function]
static void ci_hdrc_host_driver_init(void)
^
CC drivers/usb/chipidea/otg_fsm.o
In file included from drivers/usb/chipidea/otg_fsm.c:34:0:
drivers/usb/chipidea/host.h:23:13: warning: 'ci_hdrc_host_driver_init'
defined but not used [-Wunused-function]
static void ci_hdrc_host_driver_init(void)
^Signed-off-by: Li Jun
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The 'otm8018b' is the Source Driver IC which is used
by 'TFT3P5079E' panel. This patch is adding the build
support for the 'otm8018b' kernel driver.Signed-off-by: Fancy Fang
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The 'otm8018b' is the Source Driver IC for 'TFT3P5079E'
mipi panel. This patch is the kernel driver for 'otm8018b'.
No backlight brightness adjustment function, since this is
not supported by imx7d sdb revb board.Signed-off-by: Fancy Fang
Signed-off-by: Frank Li -
Create a new dts for the 'TFT3P5079E' mipi panel on
imx7d sabresd revb board.Signed-off-by: Fancy Fang
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fix the potential integer overflow issue found by coverify.
Signed-off-by: Han Xu
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fix the raw_buffer pointer double free issue found by coverify.
Signed-off-by: Han Xu
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To avoid touch other bits of HW_ANADIG_SNVS_MISC_CTRL , use set/clear register
, and correct the bit29 setting:
--before: write 1 to toggle DDR power pin to high before enter DDR retention,
and write 1 again to pull pin to low when exit from DDR retention.
--now: write 1 to pull DDR power pin to high and write 0 to low.Signed-off-by: Robin Gong
19 May, 2016
1 commit
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The head list may be corrupted when two requests from
the same 'pxp_chan' are issued sequentially. So change
the issue_pending function to strictly serialized the
requests to avoid this kind of issue.Signed-off-by: Fancy Fang
(cherry picked from commit 3ed71dcdd8ceeb3725399053f31c1930d2e7a08d)
16 May, 2016
2 commits
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This dts is only for USB HSIC controller test which needs
Validation Port Card on it.Disable controller 3 due to strange signal on it at arm2 board.
Signed-off-by: Peter Chen
(cherry picked from commit 8bd0739d81719ed8a09ca4e45393bb1c5ce3de83) -
This piece of code is existed at imx_3.10, but missing at imx_3.14 and
imx_4.1, port it from imx_3.10.Signed-off-by: Peter Chen
(cherry picked from commit 901f278a08baf6e5109bcf538f1f78cdbbccd389)
11 May, 2016
6 commits
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Add csis-clk-settle property to imx7D SDB mipi csi.
Signed-off-by: Sandor Yu
(cherry picked from commit 01365628fdfadc4f8343722a2d5c69d5d8037540) -
Add clk_settle variable to compliance more mipi sensor.
Mipi controller should setting by followed value
according mipi sensor support D-phy version.Slave Clock Lane Control Register for TCLK-SETTLE.
2'b0x = 110 ns to 280ns (v0.87 to v1.00)
2'b10 = 150 ns to 430ns (v0.83 to v0.86)
2'b11 = 60 ns to 140ns (v0.82)Signed-off-by: Sandor Yu
(cherry picked from commit 928103ba7d28a7dbddf950892cb9d49ec2b192d3) -
ov5647 mipi camera sensor is replaced by ov5640
on imx7D SDB RevB board.Signed-off-by: Sandor Yu
(cherry picked from commit aef2ab14e91ccd173086a9849cf64619e078ed6f) -
Combine csi image setting function for 32-bit,16-bit,8-bit format.
For parallel 8-bit sensor input, when bit per pixel is 16,
csi image width should been doubled.
But for mipi input, the csi image width and height should align
with mipi whatever data width.Signed-off-by: Sandor Yu
(cherry picked from commit caa8725e713691b42aa112a6e51f12e7d595f139) -
-Support no power and reset pins platform.
-Remove specific power and reset pin setting for ov5640 daughter card.
-Put sensor in software power down state when streamoff.
-Remove unsupported video modes, keep 640x480, 720x480, 720p, 1080p 30fps
video modes in driver.Signed-off-by: Sandor Yu
(cherry picked from commit 6a6c44e2406dcd9481e3103ca2710a319265c52a) -
GPIO0~GPIO7 part:
- Commit(c8cabda5ab07) add some wrong input sel value for uart, return
them to origin setting.
- Add uart DTE pin mode setting.UART2_TX_DATA pin part:
- RM doc "iMX7D_RM_Rev0_Approval.pdf" (2016.04.25 updated in compass)
updated input sel define for UART2_RX_DATA, then set the correct input
sel for the pin.Signed-off-by: Fugang Duan
(cherry picked from commit: 90a8b06b9735dd5b8d2023ff3b95886441e0e8d9)
09 May, 2016
2 commits
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On i.MX7D, per design team's require, need to make sure
DLL is locked after DDR frequency scaled done. Although
normally there should be no issue, but it is better to
add it.Signed-off-by: Anson Huang
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On i.MX7D lpddr3, retention mode exit flow should restore
more registers to make sure the ddr controller and ddr phy
settings restored properly, otherwise, some of the boards
can NOT pass memtester after retention mode exited.Signed-off-by: Anson Huang
08 May, 2016
2 commits
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i.MX7D TO1.2 removes the DDR PAD retention mode setting
in IOMUXC GPR, it is same as TO1.0, so only apply the
IOMUXC GPR setting for TO1.1.Signed-off-by: Anson Huang
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i.MX7D 19x19 LPDDR2 ARM2 board's uSDHC1 CD pin should be
LOW active, correct it.Signed-off-by: Anson Huang
06 May, 2016
2 commits
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When A7 platform is in low power mode while M4 is NOT,
M4 should be able to send message to wake up A7, so
MU must be always as wake up source.Signed-off-by: Anson Huang
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Change when A7 signal M4 to make sure busfreq is
always up when the M4 send high bus release.
This prevents race condition for Low Power DemoSigned-off-by: Teo Hall
04 May, 2016
4 commits
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Validity bit is set in default, which means the data is not reliable,
The receive device may drop this data. So clear it in default, and
provide a mixer interface for user to control this bit.Signed-off-by: Shengjiu Wang
(cherry picked from commit 48293e6bf7793de01678ee1426cccc9119998ba1) -
Remove the pre-processing and post-processing table. use proc_autosel()
to select proper parameters.
Unify the supported input and output rate.Signed-off-by: Shengjiu Wang
(cherry picked from commit 8353ec20bd9950ec98d76423c62321a7ea0c7190) -
After the suspend/resume, hw_params may be called in bias_level is not
BIAS_ON, then the PLL is not disable/enabled, if the sample rate is
changed, the output clock is not correct.Signed-off-by: Shengjiu Wang
(cherry picked from commit cced8358c2202824dfdc1780609539655ae5fec5) -
After suspend and resume, the wm8960 codec will change the state from
BIAS_OFF to BIAS_ON, in this time, the hw_free is called, the PLL will be
diabled, and next instance is started in rapid sequence, hw_params is called
But PLL is not enabled, because the bias state is not BIAS_ON.As PLL is disabled in BIAS_ON->BIAS_STANDBY, so don't need to disable pll
in hw_free of machine driver.Signed-off-by: Shengjiu Wang
(cherry picked from commit 9b6063efd3966266a1a7616c11b818139933497e)
29 Apr, 2016
5 commits
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i.MX7d MAC1_ADDR fuse offset address is 0x640, i.MX6q/dl/sx/ul
MAC1_ADDR fuse offset address is 0x620. Correct it for i.MX7d,
otherwise read un-correct MAC address.Signed-off-by: Fugang Duan
(cherry picked from commit:74ee5313534dd9453601f4428c4916d46405669f) -
Set bcmdhd as build in type.
Signed-off-by: Haibo Chen
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Bcmdhd wifi driver default build as module, now default build in
this wifi driver. To support this build in feature, this patch
add flag ENABLE_INSMOD_NO_FW_LOAD, and use extern function
sdio_reset_comm() as instead.Signed-off-by: Haibo Chen
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This patch add function sdio_reset_comm() to support bcmdhd wifi
dirver build-in type.Signed-off-by: Haibo Chen
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i.MX7D TO1.2 fix the CKE issue, need to follow TO1.0's
precedure for DRAM frequency scaling.Signed-off-by: Anson Huang
20 Apr, 2016
1 commit
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For imx6sx-sabreauto board, the usdhc4 is used for the sd slot locate on the
base board, so need to improve the pad drive strength, otherwise we will meet
many CRC error or timeout error when insert a sd card.Signed-off-by: Haibo Chen
(cherry picked from commit 1cbfce01e4e076d7f7e3b879c2c41d217d8afa48)
19 Apr, 2016
1 commit
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SRTC needs to be kept enabled during system poweroff,
SNVS_LP control register bit 0 SRTC_ENV must be set
to enable RTC, for software poweroff, kernel just
read the register offset and value from dtb and write
to SNVS_LP control register to poweroff system, need
to make sure bit 0 SRTC_ENV is set to enable RTC during
system poweroff.Previous setting did NOT enable it which will cause
RTC stop running if using software poweroff.Signed-off-by: Anson Huang