15 Jan, 2016
40 commits
-
free pair after allocating m2m failed. Reported by coverity.
Signed-off-by: Zidan Wang
(cherry picked from commit 237a35db5b48b78250a019f891d9d746c3411d49) -
null check substream before using it. Reported by coverity.
Signed-off-by: Zidan Wang
(cherry picked from commit fad2b9c1285a34eab0dec9f90edc06ec94e70a61) -
wm8960, hdmi can't be used together for they use same SAI interface.
Which is hardware limitation.Signed-off-by: Shengjiu Wang
(cherry picked from commit 56514bac9745ec263b84adc0479c0c0314902ab9) -
EPDC_DATA14 (can be used as CAN_STBY for flexcan) is also shared with EPDC.
To make EPDC work, need move it from hog pinctrl group to its own pinctrl
group to avoid the conflict.Signed-off-by: Robby Cai
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Disable sii902x to avoid pin conflict
Signed-off-by: Robby Cai
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According to schematic, the pad used for CAN STBY signal
should be EPDC_DATA14, not GPIO1_IO07. So correct it.
And due to pin is conflict with epdc, so we also update
the imx7d-sdb-epdc.dts.Reported-by: Peng Fan
Signed-off-by: Dong Aisheng
(cherry picked from commit 9036478549729580a89db90835ee5c688acbc282)Conflicts:
arch/arm/boot/dts/imx7d-sdb.dts -
After coverity code check, it tips:
unsigned_compare: This less-than-zero comparison of an unsigned value is never trueInterrupt variable must be signed type.
Signed-off-by: Fugang Duan
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i2c device client shouldn't be freed by i2c device driver, there have
problems in below cases:
- one device match to different drivers, the second matched driver will
cannot access i2c device client if it is freed by the first matched driver.
- one module driver insmod: the first insmod fail free client due to system
low memory, after kswapd system free pages and has enough free pages, the
second insmod will cause match failed.Signed-off-by: Fugang Duan
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For i.MX6UL and i.MX7D, ddr delay logic enable bit is changed from i.MX6SX.
If want to enable qspi ddr mode, ddr delay logic should be enabled.Signed-off-by: Peng Fan
(cherry picked and merge from commit f28986825a7be1cbf2b5103ea110db28c96e74c7)
Signed-off-by: Han XuConflicts:
drivers/mtd/spi-nor/fsl-quadspi.c -
We already know that pll2_bus is the best parent of QSPI clock. Let's
set it up in clock initialization as the default, so that we can save
those implicit parent switching and rate changing calls from clock
framework.shawn.guo: cherry-pick commit ecef6a715f1a from imx_3.10.y
Signed-off-by: Shawn Guo
(cherry picked and merge from commit dd32f1868a7c00c2d69424a14e48989d9c5bf103)
Signed-off-by: Han XuConflicts:
arch/arm/mach-imx/clk-imx6sx.c -
add two more commands support for qspi on kernel 4.1, read EVCR and
write EVCR.Signed-off-by: Han Xu
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If the master mtd does not have any slave mtd partitions,
and its numeraseregions is one(only has one erease block), and
we attach the master mtd with : ubiattach -m 0 -d 0We will meet the error:
-------------------------------------------------------
root@freescale ~$ ubiattach /dev/ubi_ctrl -m 0 -d 0
UBI: attaching mtd0 to ubi0
UBI error: io_init: multiple regions, not implemented
ubiattach: error!: cannot attach mtd0
error 22 (Invalid argument)
-------------------------------------------------------In fact, if there is only one "erase block", we should not
prevent the attach.This patch fixes it.
Signed-off-by: Huang Shijie
(cherry picked from commit 361cdc47fc4c4db31c5485560cdabd94f409bd81)
(cherry picked from commit ebee7d74914fad3cf7223af84496811c9d2488a1) -
The type of new->size is unsigned long and the type of tr->blksize is int,
the result of 'new->size * tr->blksize' may exceed ULONG_MAX on 32bit
machines.Take nand chip MT29F32G08CBADBWP which is 4GB for example. The parameters
passed to kernel is 'mtdparts=gpmi-nand:-(user)', the whole nand chip will be
treated as a 4GB mtd partition. new->size is 0x800000 and tr->blksize is
0x200, 'new->size * tr->blksize' however is 0. This is what we do not want
to see.Type cast new->size to u64 to fix the multiplication overflow issue.
Signed-off-by: Peng Fan
(cherry picked from commit 5e3aae04da7488ebb02cb22810ccd3e30226cf3f) -
add the pinctrl-1 for iomux in ecspi device tree to avoid conflict.
Signed-off-by: Han Xu
(cherry picked from commit edacd0568487815ca3a0821c25912133cb6c1731) -
The LPSR turns off the power for IOMUX when suspending so restore the
IOMUX when resuming.Signed-off-by: Han Xu
(cherry picked from commit 906d0c1381e865dc7c96a4bde6fe694f1ce089a9) -
Enable qspi IOMUX sleep state for imx7d-12x12-lpddr3-arm2.
Signed-off-by: Han Xu
(cherry picked from commit 73773c936b0c33e6e01e14c646749dfa3daaedad) -
the obsolete bit DDR_EN on 6UL and 7D should be clear in case other
program set the bit and cause qspi probe fail.Signed-off-by: Han Xu
(cherry picked from commit d8b51cc358780f68e732522ee9bd6bd578dd6771) -
Enable DDR quad mode for Macronix qspi chip mx25l51245g by setting Quad
bit in status register and enabling in dts file.The LUT for SPINOR_OP_READ_1_4_4_D was initially designed for Spansion
qspi chip, so there is one cycle for "mode" after address and before
dummy. While Macronix qspi chip doesn't have this feature, so we just
take off one cycle in dts file to bypass this problem.Signed-off-by: Han Xu
(cherry picked and merge from commit e03fdad1c7713a7db70112e00c4ae96848accd34) -
Enable DDR Quad mode for QSPI on 6UL ARM2 and 7D ARM2 board to improve
the performance.Signed-off-by: Han Xu
(cherry picked and merge from commit ba6c2f00b5b000996bf8acbbd62c30d8f8f61182) -
enabled 4 qspi chips on imx7d-12x12-lpddr3-arm2 board in dts
Signed-off-by: Han Xu
(cherry picked from commit a4e10bf5e94d883c06f41b2c61f80ce23946612b) -
Add a new entry for MX25L51245G QSPI NOR chip.
Signed-off-by: Han Xu
(cherry picked from commit 9f3f15ad1b0461d6b638c34599dd74d9c43fa01f) -
Add a new dts file for QSPI on i.MX7D SDB, also changed dtb file order
to alphabetical order.Signed-off-by: Han Xu
(cherry picked and merge from commit b24b9f69616f3d603f70740543e83ea71585c0ea) -
Add new dts file for NAND on i.MX7D
Signed-off-by: Han Xu
(cherry picked and merge from commit 1464059618af514f211343d9f1cdd94999be705e) -
add new dts to support spi-nor on imx6qp sabreauto
Signed-off-by: Han Xu
(cherry picked and merge from commit edb500d09c08effce28f8c45490372f38b037815) -
create a new dts file for QSPI verification on i.MX7D
Signed-off-by: Han Xu
(cherry picked and merge from commit 2888c54189b6126519cf4c05094891980f321917) -
dts for gpmi nand and weim nor support for imx6qp sabreauto
Signed-off-by: Han Xu
(cherry picked and merge from commit adb9c42a8be0bd148069540b089d2e762bec05e9) -
disable gpmi nand module in imx6qdl default dts since it conflicts with
uart3Signed-off-by: Allen Xu
(cherry picked from commit 54105e0ad2a4e30c5c048b5b9b233e49b4fba47d) -
NAND scans the bad blocks during kernel boots up, which invokes the
gpmi_ecc_read_oob function to check the badblock mark for each block. In
this function the oob data was raw read from NAND chip without ECC, so
it hardly to guarantee the consistency of the data considering the
possible bitflips. It found that in some MLC NAND the oob data changed
and consequently the BBT changed in different power cycles. This issue
may cause the UBIFS mount failed.To fix this issue, add "nand_on_flash_bbt" option in dts to store the BBT
in NAND flash. On the first time kernel boot up, all bad blocks and
probably some fake bad block would be recognized and be recorded in
on-nand bad block table. From the second time boot, kernel will read BBT
from NAND Flash rather than calling gpmi_ecc_read_oob function to check
bad block.No bad block would be missed when create BBT since the probability that
16bit bad block mark filps from 0x00 to 0xFF is extremely low.Signed-off-by: Allen Xu
(cherry picked and merge from commit d957353768a1b6d39b340b9d10b22fc42b0aa8e2)
(cherry picked from commit 7b7d3d683a24b23f33d6c08874f31fe50ef2fc76) -
Add ddrsmp parameter to device tree for i.MX6SX Sabreauto/Sabresd board.
DDRSMP value:
0 ---- i.MX6SX Sabresd board (RevB and RevA)
2 ---- i.MX6SX Sabreauto boardThe Sabresd RevA board also needs to reduce clock to 29Mhz according to
the Spansion spec.Signed-off-by: Han Xu
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Since QSPI internal DDR sample point is relevant with board layout,
we can't use same value for all boards. Add ddrsmp parameter to device
tree for different i.MX6SX board.Signed-off-by: Ye.Li
(cherry picked and merge from commit c9115cc22d836b5b980ca20932a005ea61b20082)
(cherry picked from commit b0d9d9ce804247ccb2842bf53d2b32f14eed0309) -
supports gpmi nand and qspi on i.mx6sx sabreauto platform.
Signed-off-by: Han Xu
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add new dts file to support ecspi on imx6q sabreauto board.
Signed-off-by: Allen Xu
(cherry picked and merge from commit ff87b56022d1d63003eff79a30bedf33271781fa) -
new dts file to support gpmi/weim on imx6q sabreauto board.
Signed-off-by: Allen Xu
(cherry picked and merge from commit d51a5439d7b996a26e842c8d4034668e4c7959ab) -
new dts file to support ecspi on imx6dl sabreauto board.
Signed-off-by: Allen Xu
(cherry picked and merge from commit 243e501dbec2b62148c6a470226abced76438eac) -
dts file to support gpmi/weim on imx6dl sabreauto board.
Signed-off-by: Allen Xu
(cherry picked and merge from commit 5a7a430325e2c104609c4e3d34d4d88dc95cc50e) -
add sdb revA board QSPI legacy support for Spansion QSPI chip.
Signed-off-by: Allen Xu
(cherry picked and merge from commit 3fd143ae78007e58d1dc45bc829b462a12b93cd2)
(cherry picked from commit 8317ae5998a20b3303a2a9209c29ab5674e09dc3) -
i.MX6SX Sabreauto board enabled both NAND and QSPI1 drivrers, and by default,
NAND driver built first in kernel compiling, and it would be load first when
Kernel brought up.Since we could not guarantee all boards mounted NAND chips, we wish the Kernel
could load QSPI driver first, when system mapped QSPI and NAND, the mtd device
index won't change dynamically, otherwise, the mfgtool may write images to the
inappropriate storage devices.The code change moved the SPI driver at the prior position of NAND driver in
Makefile to solve this issue.Signed-off-by: Allen Xu
(cherry picked from commit 3d2d5724f7a2968b40c2ea0a70c09a3214da1496)
(cherry picked from commit b03ee70fdd1dfaa3be61817eb49d01d49cb107d3) -
Add new dts file to support NAND for imx6sx 19x19 arm2 board.
Signed-off-by: Allen Xu
(cherry picked and merge from commit bdc522d1773156f03b74d4711a60f81824184b40) -
The uboot may run the QuadSpi controler with command:
#sf probeSo we should reset the module in the probe.
This patch also clear the pending interrupts which arised by the uboot
code.Signed-off-by: Huang Shijie
Signed-off-by: Frank Li
Signed-off-by: Brian Norris -
QSPI1 cannot wake up CCM from WAIT mode on SX ARD board, add pmqos to
let PM NOT enter WAIT mode when accessing QSPI1, refer to TKT245618.Signed-off-by: Frank Li
Signed-off-by: Han Xu
Signed-off-by: Brian Norris
