14 Aug, 2020
1 commit
29 May, 2020
1 commit
-
Correct mhdp files copyright.
Signed-off-by: Sandor Yu
Reviewed-by: Robby Cai
(cherry picked from commit b416342c2d04e2bf4bc8b5f75b7c9999b6f08f9f)
28 May, 2020
2 commits
-
HDMI modules will be reset when device enter suspend,
and registers status will lost.
Add resume function to recovery HDMI INT/I2C/HPD registers status.Signed-off-by: Sandor Yu
-
CEC interrupt status/mask and logical address registers
will be reset when device enter suspend.
It will cause cec failed to work after device resume.
Add cec suspend/resume functions, save these registers status
when suspend and restore them when resume.Signed-off-by: Sandor Yu
27 May, 2020
1 commit
-
The crtc_states could be got concurrently if multiple atomic checks
happen simultaneously, so ERR_PTR(-EDEADLK) could be returned from
drm_atomic_get_crtc_state(). In such normal cases, we just rollback
all added drm objects and userspace could try the same atomic check
or commit again, so it's unnecessary to warn.Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu
(cherry picked from commit e72359e9308b1bbb30f604ed6118c9216f9c43fd)
22 May, 2020
1 commit
-
Apparently, in order to enable the MIPI block, the reset signals must
be in asserted mode, in order to proper de-assert and initialize the
MIPI block. So, before the enable process, assert all the MIPI resets.Signed-off-by: Robert Chiras
21 May, 2020
1 commit
-
Add copyright
Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta
19 May, 2020
1 commit
-
During the unbind() procedure, drm_encoder_cleanup() will
detach the downstream DSI bridge if exists. And the DSI
bridge's detach() will detach itself from the DSI host.
So DSI host should be unregistered later than DSI device
detach. Otherwise, below kernel panic happens:[ 2.437740] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000007
[ 2.446534] Mem abort info:
[ 2.449327] ESR = 0x96000004
[ 2.452401] EC = 0x25: DABT (current EL), IL = 32 bits
[ 2.457717] SET = 0, FnV = 0
[ 2.460777] EA = 0, S1PTW = 0
[ 2.463921] Data abort info:
[ 2.466808] ISV = 0, ISS = 0x00000004
[ 2.470649] CM = 0, WnR = 0
[ 2.473617] [0000000000000007] user address but active_mm is swapper
[ 2.479978] Internal error: Oops: 96000004 [#1] PREEMPT SMP
[ 2.485550] Modules linked in:
[ 2.488609] CPU: 0 PID: 188 Comm: kworker/0:2 Not tainted 5.4.24-04902-g14319eb2bae3 #1683
[ 2.496871] Hardware name: NXP i.MX8MPlus EVK board (DT)
[ 2.502188] Workqueue: events deferred_probe_work_func
[ 2.507328] pstate: 80000005 (Nzcv daif -PAN -UAO)
[ 2.512121] pc : mipi_dsi_detach+0x10/0x38
[ 2.516219] lr : adv7533_detach_dsi+0x18/0x30
[ 2.520574] sp : ffff80001242b6e0
[ 2.523885] x29: ffff80001242b6e0 x28: ffff8000119d6000
[ 2.529196] x27: 0000000000000000 x26: 00000000fffffdfb
[ 2.534507] x25: 0000000000000001 x24: ffff8000115159f0
[ 2.539819] x23: ffff000176652120 x22: ffff800011b94000
[ 2.545132] x21: ffff000177882000 x20: ffff0001778766e8
[ 2.550444] x19: ffff000177876880 x18: 0000000000000000
[ 2.555756] x17: ffff800011e0d000 x16: 0000000000000000
[ 2.561068] x15: 0000000000000004 x14: ffffffffffffffff
[ 2.566381] x13: 0000000000000000 x12: ffff0001745765c8
[ 2.571694] x11: ffff000174576480 x10: 0000000000000040
[ 2.577006] x9 : ffff000176020e98 x8 : ffff000176020e90
[ 2.582318] x7 : 0000000000000001 x6 : 0000000000000001
[ 2.587630] x5 : 0000000000000000 x4 : 0000000000000000
[ 2.592943] x3 : ffff800011a398b0 x2 : ffffffffffffffff
[ 2.598255] x1 : ffff0001778d5c00 x0 : ffff0001778d6400
[ 2.603569] Call trace:
[ 2.606018] mipi_dsi_detach+0x10/0x38
[ 2.609769] adv7511_bridge_detach+0x6c/0x80
[ 2.614041] drm_bridge_detach+0x2c/0x50
[ 2.617964] drm_encoder_cleanup+0x2c/0xa0
[ 2.622063] imx_sec_dsim_unbind+0x50/0x68
[ 2.626159] component_unbind.isra.0+0x2c/0x50
[ 2.630601] component_bind_all+0x1e0/0x228
[ 2.634784] imx_drm_bind+0xb8/0x150
[ 2.638357] try_to_bring_up_master+0x164/0x1c0
[ 2.642887] __component_add+0xa0/0x168
[ 2.646721] component_add+0x10/0x18
[ 2.650297] lcdifv3_crtc_probe+0x4c/0x78
[ 2.654309] platform_drv_probe+0x50/0xa0
[ 2.658317] really_probe+0xd4/0x318
[ 2.661891] driver_probe_device+0x54/0xe8
[ 2.665991] __device_attach_driver+0x80/0xb8
[ 2.670348] bus_for_each_drv+0x74/0xc0
[ 2.674183] __device_attach+0xdc/0x138
[ 2.678020] device_initial_probe+0x10/0x18
[ 2.682204] bus_probe_device+0x90/0x98
[ 2.686042] device_add+0x378/0x648
[ 2.689531] platform_device_add+0xfc/0x228
[ 2.693718] imx_lcdifv3_probe+0x2b0/0x388
[ 2.697814] platform_drv_probe+0x50/0xa0
[ 2.701825] really_probe+0xd4/0x318
[ 2.705403] driver_probe_device+0x54/0xe8
[ 2.709502] __device_attach_driver+0x80/0xb8
[ 2.713859] bus_for_each_drv+0x74/0xc0
[ 2.717696] __device_attach+0xdc/0x138
[ 2.721535] device_initial_probe+0x10/0x18
[ 2.725721] bus_probe_device+0x90/0x98
[ 2.729555] deferred_probe_work_func+0x64/0x98
[ 2.734089] process_one_work+0x198/0x320
[ 2.738100] worker_thread+0x1f0/0x420
[ 2.741850] kthread+0xf0/0x120
[ 2.744993] ret_from_fork+0x10/0x18
[ 2.748573] Code: aa0003e1 f9400000 f9400402 b4000102 (f9400442)
[ 2.754667] ---[ end trace 756e3cdcc6c5557e ]---Signed-off-by: Fancy Fang
(cherry picked from commit ac040846d4c80c03e7ccb96a3b8553f84b743d39)
15 May, 2020
4 commits
-
The YUV formats were removed from graphics plane and RGB ones were removed from
video planes. That's because, in general, one will use a window manager and the
UI will always reside on the graphics plane, while video playback will go to
the overlay planes.However, this move affects users using custom applications that would like to
use 2 graphics planes and one video plane. Or 3 graphics planes.DCSS is perfectly capable of scanning out RGB/YUV linear formats on all 3
pipes. Only tiled and tiled-compressed formats need special treatment:
tiled-compressed graphics has to always go to pipe 1 (since DEC400D is needed
for uncompressing the graphics format) whilst tiled-uncompressed and
tiled-compressed VPU formats need to always go to pipes 2 and 3 (DTRC will
handle de-tiling and decompression).Signed-off-by: Laurentiu Palcu
Reviewed-by: Robert Chiras -
Move the controller enablement from atomic plane update to
the CRTC's atomic enable, since some bridge(e.g. IT6263)
requires data stream from CRTC to be ready for its config.But this controller enablement change won't cause any side
effect, since the CRTC enable and plane update can be done
in one frame interval and to next frame all configurations
can take effect, which has the same behavior as before.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying
(cherry picked from commit ea4f7e2d01e9dde69a34a3e2f0a4d194f60080d2) -
After the atomic plane update, the shadow load should be
enabled to make sure its update can take effect on next
frame in any cases. And this enable is better to be done
in CRTC's atomic_flush() which is called after plane's
atomic_update() is called.Besides, the shadow load enable in controller enable is
unnecessary, so remove it.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying
(cherry picked from commit bfa7236c8477e8993f074a3068ddc64c1614db06) -
Combine pvi and pai power up/down functions to pavi_powerup/down
function. Move clock enable/disable function to power function.Signed-off-by: Sandor Yu
09 May, 2020
4 commits
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This patch adds runtime PM support for i.MX8qxp LDB encoder driver.
Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu -
This patch adds runtime PM support for i.MX8qm LDB encoder driver.
Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu -
This patch adds runtime PM support for i.MX8mp LDB encoder driver.
Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu -
This patch adds runtime PM support for the Freescale i.MX LDB bridge driver.
Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu
07 May, 2020
5 commits
-
This patch creates platform specific LDB encoder drivers for
i.MX53, i.MX6qdl, i.MX8qm, i.MX8qxp and i.MX8mp. The encoders
would attach the bridge added in Freescale i.MX LVDS display
bridge driver. This way, the platform specific things can be
handled in different drivers, like special phy settings, clocks
and SCU misc settings, etc.Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu -
This patch adds Freescale i.MX LVDS display bridge driver.
The driver would add a common drm bridge which can be attached
to platform specific LDB encoder drivers.Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu -
Instead of looking at ldb_ctrl to determine whether split mode is
enabled or not, we may cache it in struct imx_ldb directly so that
it can be accessed easily.Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu -
Both of the two LVDS channels should be disabled for split mode
in enc->disable().Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu -
No one is using the LVDS_BIT_MAP_SPWG/JEIDA enums, so remove them.
Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu
30 Apr, 2020
1 commit
-
Due to limited video PLL frequency points on i.MX8mp, the exact pixel clock
rate of a panel's video mode is likely unsupported by the clock tree.
The driver would take a slightly fixed up pixel clock rate to match with
the clock tree capability and the panel should still work with that.
This should work based on the agreement that the chosen panel should work
with the existing PLL frequency points.Signed-off-by: Liu Ying
Reviewed-by: Fancy Fang
29 Apr, 2020
1 commit
-
Support HBR and 6 channel.
For HBR, it only support compressed bitstream, sample rate
is 192kHz, and 8 channels.Signed-off-by: Shengjiu Wang
Reviewed-by: Viorel Suman
28 Apr, 2020
1 commit
-
The dpu common driver creates a irq chip for dpu irqs.
The parent of the irq chip on the i.MX8qm/qxp SoC is the irqsteer.
Since the irqsteer driver may support runtime PM, the dpu common
driver needs to call irq_chip_pm_get/put() where necessary to make
sure power of the irq chip is enabled/disabled properly. This
patch enables the power at the driver probe stage and disables it
at driver remove stage to achieve basic power management support
for the irq chip.Suggested-by: Andy Duan
Signed-off-by: Liu Ying
Reviewed-by: Fugang Duan
27 Apr, 2020
4 commits
-
The component framework follows a rule that 'one component bind
fails, all components fail'. So when no panel or bridge device
attached to DSIM, if return error to component core during bind
process, all the other added components also cannot be bound.Normally, this logic is reasonable for usages. But sometimes, if
there exists more than one independent display pipelines, and
one device does not exist in one pipeline will cause displays
in other pipelines also fail.So in order to support this kind of cases, even if no panel and
bridge attached, return zero to make component core believe it
is bound successfully.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying -
The panel ptr variable should be NULL in the DSI host's
detach() hook instead of in the unbind() to fix below
warning:[ 2.322570] ------------[ cut here ]------------
[ 2.327193] WARNING: CPU: 0 PID: 188 at drivers/gpu/drm/bridge/sec-dsim.c:560 sec_mipi_dsim_host_detach+0x28/0x38
[ 2.337452] Modules linked in:
[ 2.340510] CPU: 0 PID: 188 Comm: kworker/0:2 Not tainted 5.4.24-04741-g8372cb5b3eec-dirty #1524
[ 2.349293] Hardware name: FSL i.MX8MP EVK (DT)
[ 2.353828] Workqueue: events deferred_probe_work_func
[ 2.358967] pstate: 00000005 (nzcv daif -PAN -UAO)
[ 2.363759] pc : sec_mipi_dsim_host_detach+0x28/0x38
[ 2.368728] lr : mipi_dsi_detach+0x24/0x38
[ 2.372823] sp : ffff80001232b5a0
[ 2.376135] x29: ffff80001232b5a0 x28: ffff8000119b6000
[ 2.381446] x27: 0000000000000000 x26: 00000000fffffdfb
[ 2.386758] x25: 0000000000000001 x24: ffff8000114f96b8
[ 2.392071] x23: ffff0001763fd810 x22: ffff0001769eb800
[ 2.397384] x21: ffff800011a256e8 x20: ffff000177909780
[ 2.402696] x19: ffff00017793a000 x18: 0000000000000010
[ 2.408008] x17: ffff800011ded000 x16: 0000000000000000
[ 2.413320] x15: 0000000000000004 x14: 73706f5f786d695f
[ 2.418632] x13: 0000000000000000 x12: ffff00017457dc28
[ 2.423945] x11: ffff00017457db60 x10: 0000000000000000
[ 2.429257] x9 : ffff000176020e98 x8 : ffff000176020e90
[ 2.434570] x7 : 00000000400c0000 x6 : 0000000000210d00
[ 2.439882] x5 : 0000000000000001 x4 : 0000000000000000
[ 2.445194] x3 : ffff00017793a0dc x2 : ffff80001073b5b8
[ 2.450504] x1 : ffff0001778e3080 x0 : 0000000000000000
[ 2.455818] Call trace:
[ 2.458266] sec_mipi_dsim_host_detach+0x28/0x38
[ 2.462885] rad_panel_remove+0x18/0x68
[ 2.466720] mipi_dsi_drv_remove+0x1c/0x28
[ 2.470818] device_release_driver_internal+0xf4/0x1c0
[ 2.475955] device_release_driver+0x14/0x20
[ 2.480226] bus_remove_device+0x118/0x128
[ 2.484323] device_del+0x13c/0x348
[ 2.487810] device_unregister+0x14/0x30
[ 2.491736] mipi_dsi_remove_device_fn+0xc/0x18
[ 2.496270] device_for_each_child+0x58/0xa0
[ 2.500539] mipi_dsi_host_unregister+0x38/0x70
[ 2.505069] sec_mipi_dsim_unbind+0x30/0x40
[ 2.509254] imx_sec_dsim_unbind+0x24/0x48
[ 2.513351] component_unbind.isra.0+0x2c/0x50
[ 2.517793] component_bind_all+0x1e0/0x228
[ 2.521976] imx_drm_bind+0xb8/0x150
[ 2.525551] try_to_bring_up_master+0x164/0x1c0
[ 2.530082] __component_add+0xa0/0x168
[ 2.533917] component_add+0x10/0x18
[ 2.537493] lcdifv3_crtc_probe+0x4c/0x78
[ 2.541504] platform_drv_probe+0x50/0xa0
[ 2.545514] really_probe+0xd4/0x318
[ 2.549088] driver_probe_device+0x54/0xe8
[ 2.553183] __device_attach_driver+0x80/0xb8
[ 2.557542] bus_for_each_drv+0x74/0xc0
[ 2.561376] __device_attach+0xdc/0x138
[ 2.565213] device_initial_probe+0x10/0x18
[ 2.569396] bus_probe_device+0x90/0x98
[ 2.573233] device_add+0x378/0x648
[ 2.576721] platform_device_add+0xfc/0x228
[ 2.580908] imx_lcdifv3_probe+0x2b0/0x388
[ 2.585003] platform_drv_probe+0x50/0xa0
[ 2.589013] really_probe+0xd4/0x318
[ 2.592592] driver_probe_device+0x54/0xe8
[ 2.596689] __device_attach_driver+0x80/0xb8
[ 2.601045] bus_for_each_drv+0x74/0xc0
[ 2.604882] __device_attach+0xdc/0x138
[ 2.608721] device_initial_probe+0x10/0x18
[ 2.612906] bus_probe_device+0x90/0x98
[ 2.616740] deferred_probe_work_func+0x64/0x98
[ 2.621274] process_one_work+0x198/0x320
[ 2.625284] worker_thread+0x1f0/0x420
[ 2.629036] kthread+0xf0/0x120
[ 2.632179] ret_from_fork+0x10/0x18
[ 2.635753] ---[ end trace f85c345edc4c5da8 ]---Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying -
Since the resets are get through kzalloc() in bind(), apparently
they should be freed in unbind() to avoid any possible memory
leak issue.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying -
The PLL clock is shared among several different devices
including LDB, and its rate has been set suitably for
all of these devices in DTB. So it is unnecessary to be
changed by LDB again.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying
23 Apr, 2020
4 commits
-
Move 'rpm_suspended' initialization to probe(), since the
bind() function may be called more one times. And between
these calls, the 'rpm_suspended' may be changed by runtime
resume/suspend.But due to asynchronous rpm mode exists and it can also
cause pending rpm requests to be canceled, so runtime
resume/suspend may not appear in pairs strictly when code
runs into the second bind().So initializing 'rpm_suspended' in bind() can mess up the
real runtime state which should be avoided apparently.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying -
If any of the components bind failed, all the devreses
allocated during component bind stage will be freed by
component framework automatically. So 'dsim_dev' will
also be freed.But the 'encoder' field of 'dsim_dev' may be accessed
in 'drm_mode_config_cleanup()' after this free. Thus,
move 'dsim_dev' allocation to probe stage to increase
its lifetime to be same as driver.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying -
The tasks done in the function 'lcdifv3_plane_deinit()' are
completely covered by 'drm_mode_config_cleanup()' which is
called if LCDIFV3 or any other component bind failed. Thus,
the 'lcdifv3_plane_deinit()' is not useful anymore.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying -
If any of the components bind failed, all the devreses
allocated during component bind stage will be freed by
component framework automatically. But the base field
of 'lcdifv3_crtc' will be accessed after this free, so
allocate 'lcdifv3_crtc' in probe stage can avoid this
kind of use-after-free issues.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying
22 Apr, 2020
3 commits
-
The structure dpu_crtc essentially contains drm crtc. If we allocate
the instance of the structure dpu_crtc with devm_kzalloc() in ->bind(),
it would be freed in case anything in dpu_crtc_init() fails after the
call for drm_crtc_init_with_planes(). However, drm_crtc_init_with_planes()
may have already added the crtc into the crtc_list. The function
drm_mode_config_cleanup() called in imx_drm_bind() as a part of it's
bailout logic would walk through the list to try to cleanup the crtc,
which would cause the use-after-free issue. This patch changes the
dpu_crtc allocation from ->bind() to ->probe() to fix the issue. And,
with this change, ->unbind() doesn't need to cleanup the crtc anymore,
since it can be done by the imx-drm core driver.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying -
The structure imx_lcdif_mux_display essentially contains drm
encoder. If we allocate the instance of imx_lcdif_mux_display(lmuxd)
with devm_kzalloc() in ->bind(), it would be freed after
drm_bridge_attach() fails. However, drm_encoder_init() may
have already added the encoder into the encoder_list.
The function drm_mode_config_cleanup() called in imx_drm_bind()
as a part of it's bailout logic would walk through the list to
try to cleanup the encoder, which would cause the use-after-free
issue. This patch changes the lmuxd allocation from ->bind() to
->probe() to fix the issue. And, with this change, ->unbind()
doesn't need to cleanup the encoder anymore, since it can be done
by the imx-drm core driver.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying -
The structure imx_ldb essentially contains drm encoder
and drm connector. If we allocate the instance of structure
imx_ldb with devm_kzalloc() in ->bind(), it would be freed after
drm_bridge_attach() or drm_panel_attach() fail. However,
drm_encoder_init() or drm_connector_init_with_ddc() may
have already added the encoder or the connector into the
encoder_list or the connector_list. The function
drm_mode_config_cleanup() called in imx_drm_bind() as a part
of it's bailout logic would walk through the lists to try to
cleanup the encoder and the connector, which would cause the
use-after-free issue. This patch changes the imx_ldb allocation
from ->bind() to ->probe() to fix the issue. And, with this
change, ->unbind() doesn't need to cleanup the encoder and
the connector anymore, since it can be done by the imx-drm core
driver.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying
17 Apr, 2020
1 commit
-
When the master imx-drm-core binding fails, component_bind_all()
in imx-drm-core ->bind() callback will unbind all bound components
first and then call drm_mode_config_cleanup(). Since the encoder
and connector(located in imx_ldb.imx_ldb_channel) are freed after
the ldb ->unbind() callback, drm_mode_config_cleanup() would
accidentally access the freed encoder and connector again. To fix
this issue, we should cleanup the encoder and connector, i.e.,
remove them from the global encoder and connector lists, in the
->unbind() callback, so that, drm_mode_config_cleanup() won't find
them again in the lists. However, we have to make sure they exist
before the cleanup in the ->unbind() callback, because imx-drm-core
->unbind() calls drm_mode_config_cleanup() first and then unbinds
all components via component_unbind_all(). Moreover, the connector
isn't created at the first place if a bridge exists, so the check
before the cleanup makes sense for this reason as well.Signed-off-by: Liu Ying
(cherry picked from commit a39bb207c172f678ce8a0aec697770dd1bdb0652)
14 Apr, 2020
1 commit
-
After attach multiple power domains, these power domains are
power on since the state is DL_FLAG_PM_RUNTIME & DL_FLAG_RPM_ACTIVE.
The action is expected by the driver to let all power domains
always on.Fixes: 583c9de66ebf(gpu: imx: Add dpu common driver support)
Reviewed-by: Liu Ying
Signed-off-by: Fugang Duan
10 Apr, 2020
3 commits
-
DPU found in i.MX8qxp SoC may drive a parallel display through
pixel link to LCDIF mux. In different mux modes, various pixel
data can be transmitted. The pixel formats can be RGB565, RGB666
and RGB888. This patch adds LCDIF mux display encoder driver support.Reviewed-by: Robert Chiras
Tested-by: Robert Chiras
Signed-off-by: Liu Ying -
DPU found in i.MX8qxp SoC may drive parallel display via
pixel link with display stream1. The pixel link MST address
of this particular display path is 1 instead of 0. So, this
patch adds DPI encoder support so as to specify the MST
address and also to enable SYNC_CTRL and pixel link MST_VLD.Reviewed-by: Robert Chiras
Tested-by: Robert Chiras
Signed-off-by: Liu Ying -
This patch adds MEDIA_BUS_FMT_RGB565_1X30_PADLO format support for
the DPU TCON unit.Reviewed-by: Robert Chiras
Tested-by: Robert Chiras
Signed-off-by: Liu Ying