28 Apr, 2013
1 commit
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This is primarily useful when there's a driver that doesn't claim clocks
properly, but the bootloader leaves them on. It's not expected to be used
in normal cases, but for bringup and debug it's very useful to have the
option to not gate unclaimed clocks that are still on.Signed-off-by: Olof Johansson
Signed-off-by: Mike Turquette
[mturquette@linaro.org: fixed up trivial merge issue]
23 Apr, 2013
1 commit
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As reported by Rob Herring[1] there were some mismatched types between
drivers/clk/ux500/clk.h and the corresponding function definitions:drivers/clk/ux500/clk-prcc.c:145:13: error: conflicting types for 'clk_reg_prcc_pclk'
drivers/clk/ux500/clk-prcc.c:155:13: error: conflicting types for 'clk_reg_prcc_kclk'[1] http://article.gmane.org/gmane.linux.ports.arm.kernel/232246
Signed-off-by: Mike Turquette
Cc: Rob Herring
Cc: Ulf Hansson
Cc: Linus Walleij
19 Apr, 2013
1 commit
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Factor out the SP810 clocking code into a separate driver,
selecting better (faster) parent at clk_prepare() time.
This is to avoid problems with clocking infrastructure
initialisation order, in particular to avoid dependency
of fixed clock being initialized before SP810. It also
makes vexpress platform OF-based clock initialisation code
unnecessary.Signed-off-by: Pawel Moll
Tested-by: Catalin Marinas
Signed-off-by: Mike Turquette
[mturquette@linaro.org: add .unprepare, FIXME comment, cleaned up code]
16 Apr, 2013
2 commits
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Calling clk-si5351 driver non-OF ready was too early. This patch
makes clk-si5351 depend on CONFIG_OF again, until things get sorted out.Signed-off-by: Sebastian Hesselbarth
Reported-by: Stephen Rothwell
Signed-off-by: Mike Turquette
[mturquette@linaro.org: fixed spelling of Stephen's name] -
The common clock api provides some helpers for clk-providers but does
not export these helpers. This hinders clk-providers to be built as modules.
This patch adds __clk_get_flags() to the list of exported symbols.Signed-off-by: Sebastian Hesselbarth
Signed-off-by: Mike Turquette
14 Apr, 2013
1 commit
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The case of PLL_TYPE_WM8750 in both these functions is missing a break
statement causing a fall-through to the default: case.Insert the missing break statements.
Signed-off-by: Tony Prisk
Signed-off-by: Mike Turquette
13 Apr, 2013
5 commits
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This commit uses the new fixed-rate support on the composite clock to
unify osc24M_fixed and osc24M clocks, so it matches the actual hardware.Signed-off-by: Emilio López
Signed-off-by: Mike Turquette
[mturquette@linaro.org: replace clk_register_gatable_osc with a call to
clk_register_composite] -
The composite clock assumes that any clock implementing the .recalc_rate
callback will also implement .round_rate and .set_rate. This is not
always true; the basic fixed-rate clock will only implement .recalc_rate
and a fixed-divider clock may choose to implement .recalc_rate and
.round_rate but not .set_rate.Fix this by conditionally registering .round_rate and .set_rate
callbacks based on the rate_ops passed in to clk_composite_register.Signed-off-by: Mike Turquette
Cc: Prashant Gaikwad
Tested-by: Emilio López
Cc: Gregory CLEMENT -
Rename all div_hw and div_ops related variables and functions to use
rate_hw, rate_ops, etc. This is to make the rate-change portion of the
composite clk implementation more generic. A patch following this one
will allow for fixed-rate clocks to reuse this infrastructure.Signed-off-by: Mike Turquette
Reviewed-by: Prashant Gaikwad
Tested-by: Emilio López
Cc: Gregory CLEMENT -
This patch adds a common clock driver for Silicon Labs Si5351a/b/c
i2c programmable clock generators. Currently, the driver does not
support VXCO feature of si5351b. Passing platform_data or DT bindings
selectively allows to overwrite stored Si5351 configuration which is
very helpful for clock generators with empty eeprom configuration.
Corresponding device tree binding documentation is also added.Signed-off-by: Sebastian Hesselbarth
Tested-by: Daniel Mack
Acked-by: Guenter Roeck
Tested-by: Michal Bachraty
Signed-off-by: Mike Turquette -
Add support for DT "fixed-factor-clock" binding to the common fixed
factor clock support.Signed-off-by: Gregory CLEMENT
Tested-by: Christian Ruppert
Signed-off-by: Mike Turquette
11 Apr, 2013
3 commits
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Notifiers may return NOTIFY_(OK|DONE|STOP|BAD). The CCF uses an
inconsistent mix of checking against NOTIFY_STOP or NOTIFY_BAD.
This inconsistency leaves errors undetected in some cases:
clk_set_parent() calls __clk_speculate_rates(), which stops when it
hits a NOTIFIER_BAD (STOP is ignored), and passes this value back to the
caller.
clk_set_parent() compares this return value against NOTIFY_STOP only,
ignoring NOTIFY_BAD returns.Use NOTIFY_STOP_MASK to detect a negative notifier return value and
document all four return value options.Signed-off-by: Soren Brinkmann
Signed-off-by: Mike Turquette -
The patch setups the first version of the clock tree for ab850x, which
is used by u8500 platforms. Mainly sysctrl clocks are used.Signed-off-by: Ulf Hansson
Tested-by: Fabio Baltieri
Signed-off-by: Mike Turquette -
The abx500 sysctrl clocks are using the ab8500 sysctrl driver to
modify the clock hardware. Sysctrl clocks are represented by a
ab8500 sysctrl register and with a corresponding bitmask.The sysctrl clocks are slow path clocks, which means clk_prepare
and clk_unprepare will be used to gate|ungate these clocks.Signed-off-by: Ulf Hansson
Signed-off-by: Mike Turquette
09 Apr, 2013
4 commits
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cpu_freq_select is used as array subscript, thus the valid value range
is 0 ... ARRAY_SIZE() - 1.Signed-off-by: Axel Lin
Signed-off-by: Mike Turquette
[mturquette@linaro.org: fixed up trivial merge issues] -
Updating the clock tree topology must be protected with the spinlock
when doing clk_set_parent, otherwise we can not handle the migration
of the enable_count in a safe manner.While issuing the .set_parent callback to make the clk-hw perform the
switch to the new parent, we can not hold the spinlock since it is must
be allowed to be slow path. This complicates error handling, but is still
possible to achieve.Signed-off-by: Ulf Hansson
Cc: Rajagopal Venkat
Signed-off-by: Mike Turquette -
Fixup the broken feature of allowing reparent of a clk to the
orhpan list and vice verse. When operating on a single-parent
clk, the .set_parent callback for the clk hw is optional to
implement, but for a multi-parent clk it is mandatory.Moreover improve the errorhandling by verifying the prerequisites
before triggering clk notifiers. This will prevent unnecessary
rollback with ABORT_RATE_CHANGE.Signed-off-by: Ulf Hansson
Cc: Rajagopal Venkat
Signed-off-by: Mike Turquette -
Split __clk_reparent into three pieces, one for doing the actual
reparent for updating the clock tree topology, one for the
COMMON_CLK_DEBUG code and one for doing the rate recalculation.This patch also makes it possible to hold the spinlock over the
update of the clock tree topology, which could not be done before
when both debugfs updates and clock rate updates was done within
the same function.Signed-off-by: Ulf Hansson
Cc: Rajagopal Venkat
Signed-off-by: Mike Turquette
05 Apr, 2013
3 commits
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clk_register will copy this information, so we can just use a normal
array and do one less dynamic allocation.Signed-off-by: Emilio López
Reviewed-by: Gregory CLEMENT
Signed-off-by: Mike Turquette -
This flag was in place to prevent important clocks from getting gated
while they had no users. Now that the UART driver supports clocks
properly, we can drop this.Signed-off-by: Emilio López
Reviewed-by: Gregory CLEMENT
Signed-off-by: Mike Turquette -
This patchset adds DT support for all the AXI, AHB, APB0 and APB1
gates present on sunxi SoCs.Signed-off-by: Emilio López
Reviewed-by: Gregory CLEMENT
Signed-off-by: Mike Turquette
04 Apr, 2013
2 commits
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Dividers which have CLK_DIVIDER_ONE_BASED set have a redundant state,
being a divider value of zero. Some hardware implementations allow a
zero divider which simply doesn't alter the frequency. I.e. it acts like
a divide by one or bypassing the divider.
This flag is used to handle such HW in the clk-divider model.Signed-off-by: Soren Brinkmann
Signed-off-by: Mike Turquette -
The use common of_clk_init() function simplifies the clock initialization
and adds handling of the DT "fixed-clock".Signed-off-by: Jean-Francois Moine
Signed-off-by: Mike Turquette
[mturquette@linaro.org: fixed $SUBJECT to reflect correct file path]
03 Apr, 2013
3 commits
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The kerneldoc comment for struct clk_mux documented the non-existent
num_clks instead of flags. Correct this.Signed-off-by: James Hogan
Signed-off-by: Mike Turquette -
Reentrancy into the clock framework is necessary for clock operations
that result in nested calls to the clk api. A common example is a clock
that is prepared via an i2c transaction, such as a clock inside of a
discrete audio chip or a power management IC. The i2c subsystem itself
will use the clk api resulting in a deadlock:clk_prepare(audio_clk)
i2c_transfer(..)
clk_prepare(i2c_controller_clk)The ability to reenter the clock framework prevents this deadlock.
Other use cases exist such as allowing .set_rate callbacks to call
clk_set_parent to achieve the best rate, or to save power in certain
configurations. Yet another example is performing pinctrl operations
from a clk_ops callback. Calls into the pinctrl subsystem may call
clk_{un}prepare on an unrelated clock. Allowing for nested calls to
reenter the clock framework enables both of these use cases.Reentrancy is implemented by two global pointers that track the owner
currently holding a global lock. One pointer tracks the owner during
sleepable, mutex-protected operations and the other one tracks the owner
during non-interruptible, spinlock-protected operations.When the clk framework is entered we try to hold the global lock. If it
is held we compare the current task against the current owner; a match
implies a nested call and we reenter. If the values do not match then
we block on the lock until it is released.Signed-off-by: Mike Turquette
Cc: Rajagopal Venkat
Cc: David Brown
Tested-by: Laurent Pinchart
Reviewed-by: Thomas Gleixner
Reviewed-by: Ulf Hansson -
Create locking helpers for the global mutex and global spinlock. The
definitions of these helpers will be expanded upon in the next patch
which introduces reentrancy into the locking scheme.Signed-off-by: Mike Turquette
Cc: Rajagopal Venkat
Cc: David Brown
Tested-by: Laurent Pinchart
Reviewed-by: Thomas Gleixner
Reviewed-by: Ulf Hansson
27 Mar, 2013
7 commits
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Include zynq clk header where init function is declared.
It removes this sparse warning:
drivers/clk/clk-zynq.c:373:13: warning: symbol
'xilinx_zynq_clocks_init' was not declared. Should it be static?Signed-off-by: Michal Simek
Signed-off-by: Mike Turquette -
During the introduction of the Allwinner SoC platforms, sunxi was
initially meant as a generic name for all the variants of the Allwinner
SoC.It was ok at the time of the support of only the A10 and A13 that
look pretty much the same; but it's beginning to be troublesome with
the future addition of the Allwinner A31 (sun6i) that is quite
different, and would introduce some weird logic, where sunxi would
actually mean in some case sun4i and sun5i but without sun6i...Moreover, it makes the compatible strings naming scheme not consistent
with other architectures, where usually for this kind of compability, we
just use the oldest SoC name that has this IP, so let's do just this.Signed-off-by: Emilio López
Signed-off-by: Mike Turquette -
This patch contains useful bits of information about the sunxi clocks
that may help and/or be interesting for current and future developers.Signed-off-by: Emilio López
Acked-by: Maxime Ripard
Signed-off-by: Mike Turquette -
This commit implements the base CPU clocks for sunxi devices. It has
been tested using a slightly modified cpufreq driver from the
linux-sunxi 3.0 tree.Additionally, document the new bindings introduced by this patch.
Idling:
/ # cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
osc32k 0 0 32768
osc24M_fixed 0 0 24000000
osc24M 0 0 24000000
apb1_mux 0 0 24000000
apb1 0 0 24000000
pll1 0 0 60000000
cpu 0 0 60000000
axi 0 0 60000000
ahb 0 0 60000000
apb0 0 0 30000000
dummy 0 0 0After "yes >/dev/null &":
/ # cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
osc32k 0 0 32768
osc24M_fixed 0 0 24000000
osc24M 0 0 24000000
apb1_mux 0 0 24000000
apb1 0 0 24000000
pll1 0 0 1008000000
cpu 0 0 1008000000
axi 0 0 336000000
ahb 0 0 168000000
apb0 0 0 84000000
dummy 0 0 0Signed-off-by: Emilio López
Acked-by: Maxime Ripard
Signed-off-by: Mike Turquette -
In clk_reg_prcmu(), clk->hw.init field is assigned with a
reference local to clk_reg_prcmu() function.This patch replaces references to clk->hw.init with calls
to __clk_get_name when called after clock registration.This patch applies on top of v3.9-rc4.
Signed-off-by: Maxime Coquelin
Acked-by: Ulf Hansson
Signed-off-by: Mike Turquette
[mturquette@linaro.org: resolved trivial merge issues] -
Commit ce4f3313b05 (clk: add table lookup to mux) caused the following build
error on imx_v4_v5_defconfig/imx_v6_v7_defconfig:arch/arm/mach-imx/clk-busy.c:172:11: error: 'struct clk_mux' has no member named 'width'
Fix it by passing the 'mask' field.
Signed-off-by: Fabio Estevam
Acked-by: Peter De Schrijver
Signed-off-by: Mike Turquette
[mturquette@linaro.org: shortened $SUBJECT line] -
Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.Signed-off-by: Prashant Gaikwad
Signed-off-by: Mike Turquette
23 Mar, 2013
3 commits
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Add a table lookup feature to the mux clock. Also allow arbitrary masks
instead of the width. This will be used by some clocks on Tegra114. Also
adapt the tegra periph clk because it uses struct clk_mux directly.Signed-off-by: Peter De Schrijver
Tested-by: Stephen Warren
Signed-off-by: Mike Turquette -
Return type of function clk_propagate_rate_change is a pointer.
But 0 was being returned. Change it to NULL.
Silences the following warning:
drivers/clk/clk.c:977:24: warning: Using plain integer as NULL pointerSigned-off-by: Sachin Kamat
Reviewed-by: Pankaj Jangra
Signed-off-by: Mike Turquette -
In case of error, the function clk_get() returns ERR_PTR()
not NULL. The NULL test in the return value check should
be replaced with IS_ERR().Signed-off-by: Wei Yongjun
Acked-by: Barry Song
Signed-off-by: Mike Turquette
[mturquette@linaro.org: added missing parenthesis to fix compile break]
22 Mar, 2013
2 commits
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This patch corrects wrongly configured parent clock for following
devices:* Video enc/decoder
* Video ip
* Pin control
* ACP
* camxSigned-off-by: Vipul Kumar Samar
Reviewed-by: Shiraz Hashim
Acked-by: Viresh Kumar
Signed-off-by: Mike Turquette -
Correcting misspelling inside the clk.txt.
Signed-off-by: Eduardo Valentin
Signed-off-by: Mike Turquette
20 Mar, 2013
2 commits
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This driver adds support for the AXI clkgen pcore to the common clock framework.
The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer
commonly found in Xilinx FPGAs.The AXI clkgen pcore is used in Analog Devices' reference designs targeting
Xilinx FPGAs.Signed-off-by: Lars-Peter Clausen
Signed-off-by: Mike Turquette -
To be able to gate unused prcmu clocks from the clk_disable_unused sequence,
clk-prcmu now implements the is_prepared callback.Signed-off-by: Ulf Hansson
Signed-off-by: Mike Turquette
