06 Aug, 2015

1 commit


25 May, 2015

1 commit

  • Not all architectures have io memory.

    Fixes:
    drivers/built-in.o: In function `spmi_pmic_arb_probe':
    spmi-pmic-arb.c:(.text+0x1ed399): undefined reference to `devm_ioremap_resource'

    Signed-off-by: Richard Weinberger
    Signed-off-by: Greg Kroah-Hartman

    Richard Weinberger
     

03 Apr, 2015

1 commit

  • Qualcomm PMIC arbiter driver already depends on ARCH_QCOM,
    which could be either ARM or ARM64. New version of the PMIC
    arbiter controller is available on 64 bit platforms.
    Remove ARM dependency to allow driver to be build for 64 bit
    platforms.

    Signed-off-by: Ivan T. Ivanov
    Signed-off-by: Greg Kroah-Hartman

    Ivan T. Ivanov
     

09 Mar, 2014

1 commit

  • With the split of Qualcomm MSM support into legacy and multiplatform,
    the SPMI PMIC arb driver is only relevant on the multiplatform supported
    SoCs. Switch the Kconfig depends to ARCH_QCOM.

    Acked-by: Kumar Gala
    Signed-off-by: Josh Cartwright
    Signed-off-by: Greg Kroah-Hartman

    Josh Cartwright
     

16 Feb, 2014

3 commits

  • The Qualcomm PMIC Arbiter, in addition to being a basic SPMI controller,
    also implements interrupt handling for slave devices. Note, this is
    outside the scope of SPMI, as SPMI leaves interrupt handling completely
    unspecified.

    Extend the driver to provide a irq_chip implementation and chained irq
    handling which allows for these interrupts to be used.

    Cc: Thomas Gleixner
    Signed-off-by: Josh Cartwright
    Signed-off-by: Greg Kroah-Hartman

    Josh Cartwright
     
  • Qualcomm's PMIC Arbiter SPMI controller functions as a bus master and
    is used to communication with one or more PMIC (slave) devices on the
    SPMI bus. The PMIC Arbiter is actually a hardware wrapper around the
    SPMI controller that provides concurrent and autonomous PMIC access
    to various entities that need to communicate with the PMIC.

    The SPMI controller hardware handles all of the SPMI bus activity (bus
    arbitration, sequence start condition, transmission of frames, etc).
    This software driver uses the PMIC Arbiter register interface to
    initiate command sequences on the SPMI bus. The status register is
    read to determine when the command sequence has completed and whether
    or not it completed successfully.

    Signed-off-by: Kenneth Heitke
    Signed-off-by: Josh Cartwright
    Signed-off-by: Greg Kroah-Hartman

    Kenneth Heitke
     
  • System Power Management Interface (SPMI) is a specification
    developed by the MIPI (Mobile Industry Process Interface) Alliance
    optimized for the real time control of Power Management ICs (PMIC).

    SPMI is a two-wire serial interface that supports up to 4 master
    devices and up to 16 logical slaves.

    The framework supports message APIs, multiple busses (1 controller
    per bus) and multiple clients/slave devices per controller.

    Signed-off-by: Kenneth Heitke
    Signed-off-by: Michael Bohan
    Signed-off-by: Josh Cartwright
    Signed-off-by: Greg Kroah-Hartman

    Kenneth Heitke