26 May, 2020
1 commit
-
There are two more DONE0_CONFIG/DONE1_CONFIG registers on i.mx8m family.
Add them to save/restore register list during systerm level suspend/
resume to restore them after resume back, otherwise, PDM case maybe failed
in suspend/resume case.Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang
(cherry picked from commit 2c213d8ac495065f5ec4182335c151d32d0eb482)
20 May, 2020
1 commit
-
The legacy terminate_worker may terminate the next transfer if it comes
before all jobs done in terminated_worker, or refuse to setup next transfer
since sdmac->desc may not be NULL in sdma_issue_pending(). That case could
be easily caught in Audio play in case underrun happen at ALSA level which
means dma channel will be terminated and start again very frequently.
So move the logic part of 'sdmac->desc' into sdma_disable_channel_async but
leave the desc free in the work to kill the above case.Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang
(cherry picked from commit acf2a79f1f73b1cf59b2e3dc096ff4340cfe7687)
07 May, 2020
3 commits
-
Add sdma_get_firmware_wait() since sdma firmware have to be ready after
runtime resume. That could be done for runtime feature on i.mx8mp since
the only sdma client audio driver request sdma channel after rootfs
mounted which means no any block in sdma_get_firmware_wait() as
sdma_get_firmware().Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang -
Add runtime suspend/resume support on i.mx8mp. So sdma will be initialized
and firmware will be loaded at first channel requested, sdma will be off
once no any channel is running.For the legacy chips just keep sdma on
always as before.Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang -
Split sdma_init_sw and sdma_init_hw from sdma_init, so that sdma_init_hw
could be delayed in channel allocate phase and it's easier for implementing
runtime suspend/resume in the next.Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang
28 Apr, 2020
2 commits
-
Add spinlock for 'tcd_pool', otherwise, in some race condition,
'tcd_pool = NULL' cause ISR never clear edma channel INT anymore which
cause interrupt storm. Besides, clear interrupt directly before poweroff
for safe.Signed-off-by: Robin Gong
Reviewed-by: Fugang Duan
(cherry picked from commit 37149f29a631f074ac65889375cd1b077284edf8) -
For rx/tx channel for audio share the same interrupt, should check INT
before clearing it directly, otherwise, audio rx may clear wrongly audio tx
channe meaningful interrupt instead of meaningless on audio rx before power
up rx edma channel.Signed-off-by: Robin Gong
Reviewed-by: Fugang Duan
(cherry picked from commit 1afea8def323ae2fadafb50264e52483b855f4bd)
10 Apr, 2020
1 commit
-
In multi audio play/stop case,sdma_alloc_chan_resources/
sdma_free_chan_resources will be called quickly, especially,dma done
interrupt comes after sdma_free_chan_resources, thus, system will be
hang in interrupt since it'll check sdma register but clocks have
already been disabled in sdma_free_chan_resources. To avoid it, enable
clock in isr.Signed-off-by: Robin Gong
(cherry picked from commit 80b0e31cdd38d77ea5b0a116fe9f2b2dec23dd2b)
19 Mar, 2020
1 commit
-
In commit 4d370a103695 ("crypto: caam - change return code in caam_jr_enqueue function"),
the return code of caam_jr_enqueue function was changed
from 0 to -EINPROGRESS, in case of success, -ENOSPC in case
the CAAM is busy (has no space left in job ring queue),
-EIO if it cannot map the caller's descriptor.Update the case for break from the loop of caam_dma_prep_memcpy
based on the new return code from caam_jr_enqueue function.Fixes: 4d370a103695 ("crypto: caam - change return code in caam_jr_enqueue function")
Signed-off-by: Iuliana Prodan
Reviewed-by: Horia Geantă
08 Mar, 2020
1 commit
-
Merge Linux stable release v5.4.24 into imx_5.4.y
* tag 'v5.4.24': (3306 commits)
Linux 5.4.24
blktrace: Protect q->blk_trace with RCU
kvm: nVMX: VMWRITE checks unsupported field before read-only field
...Signed-off-by: Jason Liu
Conflicts:
arch/arm/boot/dts/imx6sll-evk.dts
arch/arm/boot/dts/imx7ulp.dtsi
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
drivers/clk/imx/clk-composite-8m.c
drivers/gpio/gpio-mxc.c
drivers/irqchip/Kconfig
drivers/mmc/host/sdhci-of-esdhc.c
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
drivers/net/can/flexcan.c
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
drivers/net/ethernet/mscc/ocelot.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
drivers/net/phy/realtek.c
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
drivers/perf/fsl_imx8_ddr_perf.c
drivers/tee/optee/shm_pool.c
drivers/usb/cdns3/gadget.c
kernel/sched/cpufreq.c
net/core/xdp.c
sound/soc/fsl/fsl_esai.c
sound/soc/fsl/fsl_sai.c
sound/soc/sof/core.c
sound/soc/sof/imx/Kconfig
sound/soc/sof/loader.c
29 Feb, 2020
1 commit
-
This reverts commit 8a7aa4feeaeabc12181e1997a298eb73d2ed2d65 which is
commit 02939cd167095f16328a1bd5cab5a90b550606df upstream.Andreas writes:
This patch breaks our imx6 board with the attached trace.
Reverting the patch makes it boot again.Reported-by: Andreas Tobler
Cc: Sascha Hauer
Cc: Robin Gong
Cc: Vinod Koul
Cc: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
28 Feb, 2020
1 commit
-
Add sdma restore back for i.mx8mp since its power resource audioimx will
be off after suspend.Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang
26 Feb, 2020
1 commit
-
Our platforms(such as LS1021A, LS1012A, LS1043A, LS1046A, LS1028A) with
below registers(CHCFG0 - CHCFG15) of eDMA as follows:
*-----------------------------------------------------------*
| Offset | OTHERS | LS1028A |
|--------------|--------------------|-----------------------|
| 0x0 | CHCFG0 | CHCFG3 |
|--------------|--------------------|-----------------------|
| 0x1 | CHCFG1 | CHCFG2 |
|--------------|--------------------|-----------------------|
| 0x2 | CHCFG2 | CHCFG1 |
|--------------|--------------------|-----------------------|
| 0x3 | CHCFG3 | CHCFG0 |
|--------------|--------------------|-----------------------|
| ... | ...... | ...... |
|--------------|--------------------|-----------------------|
| 0xC | CHCFG12 | CHCFG15 |
|--------------|--------------------|-----------------------|
| 0xD | CHCFG13 | CHCFG14 |
|--------------|--------------------|-----------------------|
| 0xE | CHCFG14 | CHCFG13 |
|--------------|--------------------|-----------------------|
| 0xF | CHCFG15 | CHCFG12 |
*-----------------------------------------------------------*This patch is to improve edma driver to fit LS1028A platform.
Signed-off-by: Peng Ma
Reviewed-by: Robin Gong
Link: https://lore.kernel.org/r/20191212033714.4090-1-peng.ma@nxp.com
Signed-off-by: Vinod Koul
(cherry picked from commit e961f8b923ecb0875178fde884f277837b08fd4f)
24 Feb, 2020
3 commits
-
[ Upstream commit 02939cd167095f16328a1bd5cab5a90b550606df ]
The current descriptor is not on any list of the virtual DMA channel.
Once sdma_terminate_all() is called when a descriptor is currently
in flight then this one is forgotten to be freed. We have to call
vchan_terminate_vdesc() on this descriptor to re-add it to the lists.
Now that we also free the currently running descriptor we can (and
actually have to) remove the current descriptor from its list also
for the cyclic case.Signed-off-by: Sascha Hauer
Reviewed-by: Robin Gong
Tested-by: Robin Gong
Link: https://lore.kernel.org/r/20191216105328.15198-10-s.hauer@pengutronix.de
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin -
[ Upstream commit dae7a589c18a4d979d5f14b09374e871b995ceb1 ]
dma_chan_to_owner() dereferences the driver from the struct device to
obtain the owner and call module_[get|put](). However, if the backing
device is unbound before the dma_device is unregistered, the driver
will be cleared and this will cause a NULL pointer dereference.Instead, store a pointer to the owner module in the dma_device struct
so the module reference can be properly put when the channel is put, even
if the backing device was destroyed first.This change helps to support a safer unbind of DMA engines.
If the dma_device is unregistered in the driver's remove function,
there's no guarantee that there are no existing clients and a users
action may trigger the WARN_ONCE in dma_async_device_unregister()
which is unlikely to leave the system in a consistent state.
Instead, a better approach is to allow the backing driver to go away
and fail any subsequent requests to it.Signed-off-by: Logan Gunthorpe
Link: https://lore.kernel.org/r/20191216190120.21374-2-logang@deltatee.com
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin -
[ Upstream commit 4b048178854da11656596d36a107577d66fd1e08 ]
There is duplicated argument to && in function fsl_qdma_free_chan_resources,
which looks like a typo, pointer fsl_queue->desc_pool also needs NULL check,
fix it.
Detected with coccinelle.Fixes: b092529e0aa0 ("dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs")
Signed-off-by: Chen Zhou
Reviewed-by: Peng Ma
Tested-by: Peng Ma
Link: https://lore.kernel.org/r/20200120125843.34398-1-chenzhou10@huawei.com
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin
15 Feb, 2020
1 commit
-
commit a5b982af953bcc838cd198b0434834cc1dff14ec upstream.
The driver misses checking the result of devm_regmap_init_mmio().
Add a check to fix it.Fixes: fc15be39a827 ("dmaengine: axi-dmac: add regmap support")
Signed-off-by: Chuhong Yuan
Reviewed-by: Alexandru Ardelean
Link: https://lore.kernel.org/r/20191209085711.16001-1-hslester96@gmail.com
Signed-off-by: Vinod Koul
Signed-off-by: Greg Kroah-Hartman
26 Jan, 2020
1 commit
-
[ Upstream commit 340049d453682a9fe8d91fe794dd091730f4bb25 ]
When devm_kcalloc fails, it forgets to call edma_free_slot.
Replace direct return with failure handler to fix it.Fixes: 1be5336bc7ba ("dmaengine: edma: New device tree binding")
Signed-off-by: Chuhong Yuan
Link: https://lore.kernel.org/r/20191118073802.28424-1-hslester96@gmail.com
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin
18 Jan, 2020
3 commits
-
[ Upstream commit b0b5ce1010ffc50015eaec72b0028aaae3f526bb ]
If dma_alloc_coherent() returns NULL in ioat_alloc_ring(), ring
allocation must not proceed.Until now, if the first call to dma_alloc_coherent() in
ioat_alloc_ring() returned NULL, the processing could proceed, failing
with NULL-pointer dereferencing further down the line.Signed-off-by: Alexander Barabash
Acked-by: Dave Jiang
Link: https://lore.kernel.org/r/75e9c0e84c3345d693c606c64f8b9ab5@x13pwhopdag1307.AMER.DELL.COM
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin -
[ Upstream commit 2f42e05b942fe2fbfb9bbc6e34e1dd8c3ce4f3a4 ]
In some cases we seem to submit two transactions in a row, which
causes us to lose track of the first. If we then cancel the
request, we may still get an interrupt, which traverses a null
ds_run value.So try to avoid starting a new transaction if the ds_run value
is set.While this patch avoids the null pointer crash, I've had some
reports of the k3dma driver still getting confused, which
suggests the ds_run/ds_done value handling still isn't quite
right. However, I've not run into an issue recently with it
so I think this patch is worth pushing upstream to avoid the
crash.Signed-off-by: John Stultz
[add ss tag]
Link: https://lore.kernel.org/r/20191218190906.6641-1-john.stultz@linaro.org
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin -
commit f27c22736d133baff0ab3fdc7b015d998267d817 upstream.
On some platforms the clock can be fixed rate, always running one and
there is no need to do anything with it.In order to support those platforms, switch to use optional clock.
Fixes: f8d9ddbc2851 ("dmaengine: dw: platform: Enable iDMA 32-bit on Intel Elkhart Lake")
Depends-on: 60b8f0ddf1a9 ("clk: Add (devm_)clk_get_optional() functions")
Signed-off-by: Andy Shevchenko
Acked-by: Viresh Kumar
Link: https://lore.kernel.org/r/20190924085116.83683-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Vinod Koul
Signed-off-by: Greg Kroah-Hartman
09 Jan, 2020
2 commits
-
commit 24461d9792c2c706092805ff1b067628933441bd upstream.
vchan_vdesc_fini() is freeing up 'vd' so the access to vd->tx_result is
via already freed up memory.Move the vchan_vdesc_fini() after invoking the callback to avoid this.
Fixes: 09d5b702b0f97 ("dmaengine: virt-dma: store result on dma descriptor")
Signed-off-by: Peter Ujfalusi
Reviewed-by: Alexandru Ardelean
Link: https://lore.kernel.org/r/20191220131100.21804-1-peter.ujfalusi@ti.com
Signed-off-by: Vinod Koul
Signed-off-by: Greg Kroah-Hartman -
commit a40c94be2336f3002563c9ae16572143ae3422e2 upstream.
It turns out that the JZ4725B displays the same buggy behaviour as the
JZ4740 that was described in commit f4c255f1a747 ("dmaengine: dma-jz4780:
Break descriptor chains on JZ4740").Work around it by using the same workaround previously used for the
JZ4740.Fixes commit f4c255f1a747 ("dmaengine: dma-jz4780: Break descriptor
chains on JZ4740")Cc:
Signed-off-by: Paul Cercueil
Link: https://lore.kernel.org/r/20191210165545.59690-1-paul@crapouillou.net
Signed-off-by: Vinod Koul
Signed-off-by: Greg Kroah-Hartman
05 Jan, 2020
2 commits
-
[ Upstream commit 41814c4eadf8a791b6d07114f96e7e120e59555c ]
platform_get_irq_byname() might return -errno which later would be cast
to an unsigned int and used in IRQ handling code leading to usage of
wrong ID and errors about wrong irq_base.Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Peng Ma
Tested-by: Peng Ma
Link: https://lore.kernel.org/r/20191004150826.6656-1-krzk@kernel.org
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin -
[ Upstream commit 8a631a5a0f7d4a4a24dba8587d5d9152be0871cc ]
Whenever we reset the channel, we need to clear desc_pendingcount
along with desc_submitcount. Otherwise when a new transaction is
submitted, the irq coalesce level could be programmed to an incorrect
value in the axidma case.This behavior can be observed when terminating pending transactions
with xilinx_dma_terminate_all() and then submitting new transactions
without releasing and requesting the channel.Signed-off-by: Nicholas Graumann
Signed-off-by: Radhey Shyam Pandey
Link: https://lore.kernel.org/r/1571150904-3988-8-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin
05 Dec, 2019
2 commits
-
create one dma_pool dedicate for all following dma_alloc and avoid
keeping allocate available memories.Signed-off-by: Han Xu
-
enable runtime PM for mxs-dma
Signed-off-by: Han Xu
03 Dec, 2019
2 commits
-
Fix the following build warning:
../drivers/dma/pxp/pxp_dma_v3.c: In function 'pxp_store_shift_ctrl_config':
../drivers/dma/pxp/pxp_dma_v3.c:1700:17: warning: this statement may fall through [-Wimplicit-fallthrough=]
shift_bypass = 1;
~~~~~~~~~~~~~^~~
../drivers/dma/pxp/pxp_dma_v3.c:1701:3: note: here
case PXP_PIX_FMT_YVYU:
^~~~
../drivers/dma/pxp/pxp_dma_v3.c:1705:17: warning: this statement may fall through [-Wimplicit-fallthrough=]
shift_bypass = 1;
~~~~~~~~~~~~~^~~
../drivers/dma/pxp/pxp_dma_v3.c:1706:3: note: here
case PXP_PIX_FMT_NV61:
^~~~Signed-off-by: Robby Cai
Reviewed-by: Sandor Yu
(cherry picked from commit c1ca344b32c914c89cbcf307a2e1313ad82a0b71) -
In case 60 seconds maybe not enough for Yocto loading sdma firmware on
some poor performance chips such as i.mx6sll in nfs case, add another
round to load firmware.Signed-off-by: Robin Gong
Reviewed-by: Fugang Duan
02 Dec, 2019
5 commits
-
* pxp/next:
media: pxp device: fix kernel dump when run pxp_test
media: v4l2: add pxp_v4l2 driver
dma: pxp: porting pxp dma driver from imx_4.19.y -
* origin/dma/sdma: (23 commits)
LF-301: dmaengine: imx-sdma: Add once more loading firmware
LF-246: dmaengine: imx-sdma: correct is_ram_script checking
MLK-23005: dmaengine: imx-sdma: correct data size of channel context
MLK-22972 dmaengine: imx-sdma: correct the script number for v3
dma: imx-sdma: Add pm_ops to support suspend & resume
... -
* origin/dma/qdma:
dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support -
* origin/dma/mxsdma:
dma: mxs-dma: change the way to register the probe function
MLK-19897: dma: mxs-dma: filter out the unrelated dma channels -
* origin/dma/edma: (23 commits)
MLK-22909 dmaengine: fsl-edma-v3: clear interrupt coming after channel terminated
MLK-22302-2: dmaengine: fsl-edma-v3: fix build warning with CONFIG_PM_SLEEP=n
MLK-22284-2 dmaengine: fsl-edma-v3: check dma description before register touch
MLK-22284-1 dmaengine: fsl-edma-v3: add power domains for each channel
MLK-21443: dmaengine: fsl-edma-v3: clear pending irq before request irq
...
29 Nov, 2019
1 commit
-
Correct is_ram_script checking in case sdma firmware not loaded as
expected, otherwise all scripts are considered as rom script without
correct "sdma firmware not ready!" since sdma->ram_code_start is 0.Note: only add the doubtless is_ram_script for sdma-imx6q.bin/sdma-imx7d.
bin , and leave the legacy i.mx5x/i.mx3x/i.mx2x firmware alone since not
sure which of the remain scripts should be in ram.Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang
25 Nov, 2019
5 commits
-
Fix compilation error, introduced by incorrect rebase of the
commit 9c51c141264c ("dma: caam: add dma memcpy driver"
on top of upstream
commit 1bcdf5a00f41 ("crypto: caam - make CAAM_PTR_SZ dynamic")Fixes: 9c51c141264c ("dma: caam: add dma memcpy driver")
Signed-off-by: Horia Geantă -
This module introduces a memcpy DMA driver based on the DMA capabilities
of the CAAM hardware block. CAAM DMA is a platform driver that is only
probed if the device is defined in the device tree. The driver creates
a DMA channel for each JR of the CAAM. This introduces a dependency on
the JR driver. Therefore a defering mechanism was used to ensure that
the CAAM DMA driver is probed only after the JR driver.Signed-off-by: Radu Alexe
Signed-off-by: Tudor Ambarus
Signed-off-by: Rajiv Vishwakarma
Signed-off-by: Horia Geantă -
DPPA2(Data Path Acceleration Architecture 2) qDMA supports
virtualized channel by allowing DMA jobs to be enqueued into
different work queues. Core can initiate a DMA transaction by
preparing a frame descriptor(FD) for each DMA job and enqueuing
this job through a hardware portal. DPAA2 components can also
prepare a FD and enqueue a DMA job through a hardware portal.
The qDMA prefetches DMA jobs through DPAA2 hardware portal. It
then schedules and dispatches to internal DMA hardware engines,
which generate read and write requests. Both qDMA source data and
destination data can be either contiguous or non-contiguous using
one or more scatter/gather tables.
The qDMA supports global bandwidth flow control where all DMA
transactions are stalled if the bandwidth threshold has been reached.
Also supported are transaction based read throttling.Add NXP dppa2 qDMA to support some of Layerscape SoCs.
such as: LS1088A, LS208xA, LX2, etc.Signed-off-by: Peng Ma
-
The MC(Management Complex) exports the DPDMAI(Data Path DMA Interface)
object as an interface to operate the DPAA2(Data Path Acceleration
Architecture 2) qDMA Engine. The DPDMAI enables sending frame-based
requests to qDMA and receiving back confirmation response on transaction
completion, utilizing the DPAA2 QBMan(Queue Manager and Buffer Manager
hardware) infrastructure. DPDMAI object provides up to two priorities for
processing qDMA requests.
The following list summarizes the DPDMAI main features and capabilities:
1. Supports up to two scheduling priorities for processing
service requests.
- Each DPDMAI transmit queue is mapped to one of two service
priorities, allowing further prioritization in hardware between
requests from different DPDMAI objects.
2. Supports up to two receive queues for incoming transaction
completion confirmations.
- Each DPDMAI receive queue is mapped to one of two receive
priorities, allowing further prioritization between other
interfaces when associating the DPDMAI receive queues to DPIO
or DPCON(Data Path Concentrator) objects.
3. Supports different scheduling options for processing received
packets:
- Queues can be configured either in 'parked' mode (default),
or attached to a DPIO object, or attached to DPCON object.
4. Allows interaction with one or more DPIO objects for
dequeueing/enqueueing frame descriptors(FD) and for
acquiring/releasing buffers.
5. Supports enable, disable, and reset operations.Add dpdmai to support some platforms with dpaa2 qdma engine.
Signed-off-by: Peng Ma
-
Clear EDMA_CH_INT in case dma done interrupt comes after channel terminated
instead of channel free-ed, otherwise, RCU maybe caught because it's
ignored without interrupt status cleared as Android team report in Monkey
test.Signed-off-by: Robin Gong
Acked-by: Fugang Duan
(cherry picked from commit ef91ff6ed465cebe2fe6483a480351abba36e237)
(cherry picked from commit 56ee55c71c5f3ef254acb4dee581e68f79ef13a5)
